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-rw-r--r--Src/osmocom-bb/src/target/firmware/include/mtk/bfe.h107
-rw-r--r--Src/osmocom-bb/src/target/firmware/include/mtk/bpi.h20
-rw-r--r--Src/osmocom-bb/src/target/firmware/include/mtk/bsi.h41
-rw-r--r--Src/osmocom-bb/src/target/firmware/include/mtk/emi.h42
-rw-r--r--Src/osmocom-bb/src/target/firmware/include/mtk/mt6139.h60
-rw-r--r--Src/osmocom-bb/src/target/firmware/include/mtk/mt6235.h74
-rw-r--r--Src/osmocom-bb/src/target/firmware/include/mtk/mt6235_sciphone_g2.h38
-rw-r--r--Src/osmocom-bb/src/target/firmware/include/mtk/system.h195
-rw-r--r--Src/osmocom-bb/src/target/firmware/include/mtk/tdma_timer.h60
9 files changed, 0 insertions, 637 deletions
diff --git a/Src/osmocom-bb/src/target/firmware/include/mtk/bfe.h b/Src/osmocom-bb/src/target/firmware/include/mtk/bfe.h
deleted file mode 100644
index b07f620..0000000
--- a/Src/osmocom-bb/src/target/firmware/include/mtk/bfe.h
+++ /dev/null
@@ -1,107 +0,0 @@
-#ifndef _MTK_BFE_H
-#define _MTK_BFE_H
-
-/* MTK Baseband Frontend */
-
-/* MT6235 Chapter 10 */
-
-enum mtk_bfe_reg {
- BFE_CON = 0x0000,
- BFE_STA = 0x0004,
- /* Rx Configuration Register */
- RX_CFG = 0x0010,
- /* Rx Control Register */
- RX_CON = 0x0014,
- /* RX Interference Detection Power Measurement Control Register */
- RX_PM_CON = 0x0018,
- /* RX FIR Coefficient Set ID Control Register */
- RX_FIR_CSID_CON = 0x001c,
- /* RX Ram0 Coefficient Set 0 Register */
- RX_RAM0_CS0 = 0x0070,
- /* RX Ram1 Coefficient Set 0 Register */
- RX_RAM1_CS0 = 0x0020,
- /* Rx Interference Detection HPF Power Register */
- RX_HPWR_STS = 0x00b0,
- /* Rx Interference Detection BPF Power Register */
- RX_BPWR_STS = 0x00b4,
-
- TX_CFG = 0x0060,
- TX_CON = 0x0064,
- TX_OFF = 0x0068,
-};
-
-#define RX_RAM0_CS(n) (RX_RAM0_CS0 + (n)*4)
-#define RX_RAM1_CS(n) (RX_RAM0_CS1 + (n)*4)
-
-/* SWAP I/Q before input to baesband frontend */
-#define RX_CFG_SWAP_IQ 0x0001
-/* Bypass RX FIR filter control */
-#define RX_CFG_BYPFLTR 0x0002
-/* Number of RX FIR filter taps */
-#define RX_CFG_FIRTPNO(n) (((n) & 0x3f) << 4)
-
-#define RX_CON_BLPEN_NORMAL (0 << 0)
-#define RX_CON_BLPEN_LOOPB (1 << 0)
-#define RX_CON_BLPEN_LOOPB_FILT (2 << 0)
-
-/* Phase de-rotation in wide FIR data path */
-#define RX_CON_PH_ROEN_W (1 << 2)
-/* Phase de-rotation in narrow FIR data path */
-#define RX_CON_PH_ROEN_N (1 << 3)
-/* RX I-data gain compenstation select (+/- 1.5dB */
-#define RX_CON_IGAINSEL_00dB (0 << 4)
-#define RX_CON_IGAINSEL_03dB (1 << 4)
-#define RX_CON_IGAINSEL_06dB (2 << 4)
-#define RX_CON_IGAINSEL_09dB (3 << 4)
-#define RX_CON_IGAINSEL_12dB (4 << 4)
-#define RX_CON_IGAINSEL_15dB (5 << 4)
-#define RX_CON_IGAINSEL_n03dB (9 << 4)
-#define RX_CON_IGAINSEL_n06dB (10 << 4)
-#define RX_CON_IGAINSEL_n09dB (11 << 4)
-#define RX_CON_IGAINSEL_n12dB (12 << 4)
-#define RX_CON_IGAINSEL_n15dB (13 << 4)
-
-/* TX_CFG */
-/* Appending Bits enable */
-#define TX_CFG_APNDEN (1 << 0)
-/* Ramp Profile Select for 8PSK */
-#define TX_CFG_RPSEL_I (0 << 1) /* 50 kHz sine tone */
-#define TX_CFG_RPSEL_II (1 << 1) /* null DC I/Q */
-#define TX_CFG_RPSEL_III (3 << 1)
-#define TX_CFG_INTEN (1 << 3) /* Interpolate between bursts */
-#define TX_CFG_MDBYP (1 << 4) /* Modulator Bypass */
-#define TX_CFG_SGEN (1 << 5) /* 540 kHz sine tone */
-#define TX_CFG_ALL_10GEN_ZERO (1 << 6)
-#define TX_CFG_ALL_10GEN_ONE (2 << 6)
-#define TX_CFG_SW_QBCNT(n) (((n) & 0x1f) << 8)
-#define TX_CFG_GMSK_DTAP_SYM_1 (0 << 13)
-#define TX_CFG_GMSK_DTAP_SYM_0 (1 << 13)
-#define TX_CFG_GMSK_DTAP_SYM_2 (2 << 13)
-
-#define TX_CON_IQSWP (1 << 0) /* Swap I/Q */
-/* GMSK or 8PSK modulation for 1st through 4th burst */
-#define TX_CON_MDSEL1_8PSK (1 << 2)
-#define TX_CON_MDSEL2_8PSK (1 << 3)
-#define TX_CON_MDSEL3_8PSK (1 << 4)
-#define TX_CON_MDSEL4_8PSK (1 << 5)
-/* Quadratur phase compensation select */
-#define TX_CON_PHSEL_0deg (0 << 8)
-#define TX_CON_PHSEL_1deg (1 << 8)
-#define TX_CON_PHSEL_2deg (2 << 8)
-#define TX_CON_PHSEL_3deg (3 << 8)
-#define TX_CON_PHSEL_4deg (4 << 8)
-#define TX_CON_PHSEL_5deg (5 << 8)
-#define TX_CON_PHSEL_n5deg (10 << 8)
-#define TX_CON_PHSEL_n4deg (11 << 8)
-#define TX_CON_PHSEL_n3deg (12 << 8)
-#define TX_CON_PHSEL_n2deg (13 << 8)
-#define TX_CON_PHSEL_n1deg (14 << 8)
-/* GMSK modulator output latenct */
-#define TX_CON_GMSK_DTAP_QB(n) (((n) & 3) << 12)
-
-#define TX_OFF_I(n) (((n) & 0x3f) << 0)
-#define TX_OFF_Q(n) (((n) & 0x3f) << 8)
-/* Double Buffering */
-#define TX_OFF_TYP_DB 0x8000
-
-#endif /* _MTK_BFE_H */
diff --git a/Src/osmocom-bb/src/target/firmware/include/mtk/bpi.h b/Src/osmocom-bb/src/target/firmware/include/mtk/bpi.h
deleted file mode 100644
index 8aa8ee5..0000000
--- a/Src/osmocom-bb/src/target/firmware/include/mtk/bpi.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _MTK_BPI_H
-#define _MTK_BPI_H
-
-/* MTK Baseband Parallel Interface */
-
-/* Chapter 9.2 of MT6235 Data Sheet */
-
-#define BPI_BUF(n) (BPI_BUF0 + ((n) * 4))
-
-#define MTK_BPI(n) (n)
-
-enum mtk_bpi_reg {
- BPI_CON = 0x0000,
- BPI_BUF0 = 0x0004,
- BPI_ENA0 = 0x00b0,
- BPI_ENA1 = 0x00b4,
- BPI_ENA2 = 0x00b8,
-};
-
-#endif /* _MTK_BPI_H */
diff --git a/Src/osmocom-bb/src/target/firmware/include/mtk/bsi.h b/Src/osmocom-bb/src/target/firmware/include/mtk/bsi.h
deleted file mode 100644
index 6f381ce..0000000
--- a/Src/osmocom-bb/src/target/firmware/include/mtk/bsi.h
+++ /dev/null
@@ -1,41 +0,0 @@
-#ifndef _MTK_BSI_H
-#define _MTK_BSI_H
-
-/* MTK Baseband Serial Interface */
-
-enum bsi_reg {
- BSI_CON = 0x0000,
- BSI_D0_CON = 0x0004,
- BSI_D0_DAT = 0x0008,
-
- BSI_ENA_0 = 0x0190,
- BSI_ENA_1 = 0x0194,
- BSI_IO_CON = 0x0198,
- BSI_DOUT = 0x019c,
- BSI_DIN = 0x01a0,
- BSI_PAIR_NUM = 0x01a4,
-
-};
-
-/* Compute offset of BSI_D0_CON / BSI_D0_DAT registers */
-#define BSI_Dn_CON(x) (BSI_D0_CON + (x * 8))
-#define BSI_Dn_CON(x) (BSI_D0_DAT + (x * 8))
-
-/* MT6235 Section 9.1.1 */
-#define BSI_CON_CLK_POL_INV (1 << 0)
-#define BSI_CON_CLK_SPD_52_2 (0 << 1) /* 26 MHz */
-#define BSI_CON_CLK_SPD_52_4 (1 << 1) /* 13 MHz */
-#define BSI_CON_CLK_SPD_52_6 (2 << 1) /* 8.67 MHz */
-#define BSI_CON_CLK_SPD_52_8 (3 << 1) /* 6.50 MHz */
-#define BSI_CON_IMOD (1 << 3)
-#define BSI_CON_EN0_LEN_SHORT (1 << 4)
-#define BSI_CON_EN0_POL_INV (1 << 5)
-#define BSI_CON_EN0_LEN_SHORT (1 << 6)
-#define BSI_CON_EN0_POL_INV (1 << 7)
-#define BSI_CON_SETENV (1 << 8)
-
-/* how the length is encoded in BSI_Dx_CON */
-#define BSI_Dx_LEN(n) ((n & 0x7f) << 8)
-#define BSI_Dx_ISB 0x8000 /* select device 1 */
-
-#endif /* _MTK_BSI_H */
diff --git a/Src/osmocom-bb/src/target/firmware/include/mtk/emi.h b/Src/osmocom-bb/src/target/firmware/include/mtk/emi.h
deleted file mode 100644
index 1818499..0000000
--- a/Src/osmocom-bb/src/target/firmware/include/mtk/emi.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * (C) 2010 by Tieto <www.tieto.com>
- * Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
- *
- * All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- */
-
-#ifndef __MTK_EMI_H_
-#define __MTK_EMI_H_
-
-/* External Memory Interface register definitions */
-#define MTK_EMI_CONA (MTK_EMI_BASE + 0x00)
-#define MTK_EMI_CONB (MTK_EMI_BASE + 0x08)
-#define MTK_EMI_CONC (MTK_EMI_BASE + 0x10)
-#define MTK_EMI_COND (MTK_EMI_BASE + 0x18)
-#define MTK_EMI_CONI (MTK_EMI_BASE + 0x40)
-#define MTK_EMI_CONJ (MTK_EMI_BASE + 0x48)
-#define MTK_EMI_CONK (MTK_EMI_BASE + 0x50)
-#define MTK_EMI_CONL (MTK_EMI_BASE + 0x58)
-#define MTK_EMI_CONM (MTK_EMI_BASE + 0x60)
-#define MTK_EMI_CONN (MTK_EMI_BASE + 0x68)
-#define MTK_EMI_GENA (MTK_EMI_BASE + 0x70)
-#define MTK_EMI_GENB (MTK_EMI_BASE + 0x78)
-#define MTK_EMI_GENC (MTK_EMI_BASE + 0x80)
-#define MTK_EMI_GEND (MTK_EMI_BASE + 0x88)
-
-#endif
diff --git a/Src/osmocom-bb/src/target/firmware/include/mtk/mt6139.h b/Src/osmocom-bb/src/target/firmware/include/mtk/mt6139.h
deleted file mode 100644
index 35458b5..0000000
--- a/Src/osmocom-bb/src/target/firmware/include/mtk/mt6139.h
+++ /dev/null
@@ -1,60 +0,0 @@
-#ifndef _MTK_MT6139_H
-#define _MTK_MT6139_H
-
-enum mt6139_band {
- MTRF_BAND_GSM850 = 0,
- MTRF_BAND_GSM900 = 1,
- MTRF_BAND_GSM1800 = 2,
- MTRF_BAND_GSM1900 = 3,
-};
-
-#define MT6139_CW0_SYNCP_SHIFT 0
-#define MT6139_CW0_SYNCPW (1 << 2)
-#define MT6139_CW0_DIEN (1 << 3)
-#define MT6139_CW0_FLT (1 << 4)
-#define MT6139_CW0_AFC_SHIFT 5
-#define MT6139_CW0_VCO_SEL (1 << 11)
-#define MT6139_CW0_GPO (1 << 12)
-#define MT6139_CW0_POR (1 << 13)
-
-#define MT6139_CW1_NFRACT_SHIFT 0
-#define MT6139_CW1_NINT_SHIFT 8
-#define MT6139_CW1_BAND_SHIFT 16
-#define MT6139_CW1_TRX_850 (1 << 18)
-
-#define MT6139_CW2_GAINTBL_SHIFT 0
-#define MT6139_CW2_MODE_SHIFT 6
-#define MT6139_CW2_AUTO_CAL (1 << 9)
-#define MT6139_CW2_DCD_AQ_SHIFT 10
-#define MT6139_CW2_DCD_AI_SHIFT 16
-
-#define MT6139_CW9_DCD_CQ_SHIFT 0
-#define MT6139_CW9_DCD_BQ_SHIFT 7
-#define MT6139_CW9_PWR_DAC_C (1 << 14)
-#define MT6139_CW9_PWR_DAC_B (1 << 15)
-#define MT6139_CW9_PWR_DAC_A (1 << 16)
-#define MT6139_CW9_AM_ENABLE (1 << 17)
-
-enum mt6139_cw2_mode {
- MODE_SLEEP = 0x0,
- MODE_WARM_UP = 0x1,
- MODE_RECEIVE = 0x3,
- MODE_TRANSMIT = 0x4,
-};
-
-#define MT6139_CW11_TX_CTL (1 << 0)
-#define MT6139_CW11_TXG_IQM (1 << 1)
-#define MT6139_CW11_TXD_IQM (1 << 2)
-#define MT6139_CW11_TX_DIV2 (1 << 3)
-#define MT6139_CW11_TX_DIV4 (1 << 4)
-#define MT6139_CW11_TXG_BUF (1 << 5)
-#define MT6139_CW11_TXD_BUF (1 << 6)
-#define MT6139_CW11_TXMODGAIN_SHIFT 7
-#define MT6139_CW11_TX_FLT_SHIFT 10
-#define MT6139_CW11_TXAPC_SHIFT 14
-#define MT6139_CW11_TXPW_SHIFT 16
-#define MT6139_CW11_TXBIAST_SHIFT 18
-#define MT6139_CW11_TXDIV_GC0 (1 << 20)
-#define MT6139_CW11_TXDIV_GC1 (1 << 21)
-
-#endif /* _MTK_MT6139_H */
diff --git a/Src/osmocom-bb/src/target/firmware/include/mtk/mt6235.h b/Src/osmocom-bb/src/target/firmware/include/mtk/mt6235.h
deleted file mode 100644
index fb9d368..0000000
--- a/Src/osmocom-bb/src/target/firmware/include/mtk/mt6235.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) 2010 by Tieto <www.tieto.com>
- * Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
- *
- * All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- */
-
-#ifndef __MT6235_H
-#define __MT6235_H
-
-/* Peripheral base addresses */
-#define MTK_EFUSE_BASE 0x80000000
-#define MTK_CONFG_BASE 0x80010000
-#define MTK_GPIO_BASE 0x80020000
-#define MTK_RGU_BASE 0x80030000
-#define MTK_EMI_BASE 0x81000000
-#define MTK_CIRQ_BASE 0x81010000
-#define MTK_DMA_BASE 0x81020000
-#define MTK_UART1_BASE 0x81030000
-#define MTK_UART2_BASE 0x81040000
-#define MTK_UART3_BASE 0x81050000
-#define MTK_GPT_BASE 0x81060000
-#define MTK_KP_BASE 0x81080000
-#define MTK_PWM_BASE 0x81090000
-#define MTK_SIM_BASE 0x810A0000
-#define MTK_RTC_BASE 0x810C0000
-#define MTK_SEJ_BASE 0x810D0000
-#define MTK_BM_BASE 0x810E0000
-#define MTK_IRDA_BASE 0x810F0000
-#define MTK_I2C_BASE 0x81100000
-#define MTK_MSDC_BASE 0x81110000
-#define MTK_NFI_BASE 0x81120000
-#define MTK_MSSDC2_BASE 0x81140000
-#define MTK_TDMA_BASE 0x82000000
-#define MTK_BSI_BASE 0x82010000
-#define MTK_BPI_BASE 0x82020000
-#define MTK_AFC_BASE 0x82030000
-#define MTK_APC_BASE 0x82040000
-#define MTK_AUXADC_BASE 0x82050000
-#define MTK_DIVIDER_BASE 0x82060000
-#define MTK_FSC_BASE 0x82070000
-#define MTK_GCU_BASE 0x82080000
-#define MTK_CSD_ACC_BASE 0x82090000
-#define MTK_SHARE1_BASE 0x820A0000
-#define MTK_IRDBG1_BASE 0x820B0000
-#define MTK_SHARE2_BASE 0x820C0000
-#define MTK_IRDBG2_BASE 0x820D0000
-#define MTK_PATCH_BASE 0x820E0000
-#define MTK_AFE_BASE 0x820F0000
-#define MTK_BFE_BASE 0x82100000
-#define MTK_PLL_BASE 0x83000000
-#define MTK_ACIF_BASE 0x83010000
-#define MTK_GMC_BASE 0x84000000
-#define MTK_G2D_BASE 0x84010000
-#define MTK_GCMQ_BASE 0x84020000
-#define MTK_CAM_BASE 0x840B0000
-#define MTK_CRZ_BASE 0x840E0000
-
-#endif
diff --git a/Src/osmocom-bb/src/target/firmware/include/mtk/mt6235_sciphone_g2.h b/Src/osmocom-bb/src/target/firmware/include/mtk/mt6235_sciphone_g2.h
deleted file mode 100644
index 74d9e7b..0000000
--- a/Src/osmocom-bb/src/target/firmware/include/mtk/mt6235_sciphone_g2.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef _SCIPHONE_G2_H
-#define _SCIPHONE_G2_H
-/* Bluelans Sciphone G2 support */
-
-/* Use of the Baseband Parallel Interface by the G2 board */
-#define HB_TX MTK_BPI(0)
-#define PCS_RX MTK_BPI(1)
-#define LB_TX MTK_BPI(2)
-#define PA_EN MTK_BPI(4)
-#define BAND_SW MTK_BPI(5)
-#define MODE_PA MTK_BPI(7)
-#define RF_VCO_EN MTK_BPI(9)
-
-#define GPIO_GPS_PWR_EN MTK_GPIO(19)
-#define GPIO_WIFI_EN MTK_GPIO(20)
-#define GPIO_OP1_EN MTK_GPIO(22)
-#define GPIO_BT_PWR_EN MTK_GPIO(39)
-#define GPIO_BT_RST MTK_GPIO(62)
-#define GPIO_USB_CHR_ID MTK_GPIO(73)
-#define GPIO_FM_SCL MTK_GPIO(46)
-#define GPIO_FM_SDA MTK_GPIO(47)
-#define GPIO_GS_SCL MTK_GPIO(48)
-#define GPIO_GS_SDA MTK_GPIO(58)
-#define GPIO_GS_EN MTK_GPIO(26)
-
-#define GPIO_GPS_EINT MTK_GPIO(42)
-
-#define EINT_HEADSET MTK_EINT(0)
-#define EINT_BT MTK_EINT(1)
-#define EINT_GPS2GSM MTK_EINT(2)
-#define EINT_WIFI MTK_EINT(3)
-
-#define CLKM_BT_32k MTK_CLKM(2)
-#define CLKM_WIFI_32k MTK_CLKM(3)
-#define CLKM_FM_32k MTK_CLKM(4)
-
-
-#endif /* _SCIPHONE_G2_H */
diff --git a/Src/osmocom-bb/src/target/firmware/include/mtk/system.h b/Src/osmocom-bb/src/target/firmware/include/mtk/system.h
deleted file mode 100644
index 4543029..0000000
--- a/Src/osmocom-bb/src/target/firmware/include/mtk/system.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * (C) 2010 by Tieto <www.tieto.com>
- * Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
- *
- * All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- */
-
-#ifndef __MTK_SYSTEM_H_
-#define __MTK_SYSTEM_H_
-
-/*
- * Configuration block section (Clock, Power Down, Version and Reset
- */
-
-/* Register definitions */
-#define MTK_CONFG_HW_VERSION (MTK_CONFG_BASE + 0x000)
-#define MTK_CONFG_FW_VERSION (MTK_CONFG_BASE + 0x004)
-#define MTK_CONFG_HW_CODE (MTK_CONFG_BASE + 0x008)
-#define MTK_CONFG_SLEEP_CON (MTK_CONFG_BASE + 0x114)
-#define MTK_CONFG_MCUCLK_CON (MTK_CONFG_BASE + 0x118)
-#define MTK_CONFG_DSPCLK_CON (MTK_CONFG_BASE + 0x11C)
-#define MTK_CONFG_IDN_SEL (MTK_CONFG_BASE + 0x200)
-#define MTK_CONFG_PDN_CON0 (MTK_CONFG_BASE + 0x300)
-#define MTK_CONFG_PDN_CON1 (MTK_CONFG_BASE + 0x304)
-#define MTK_CONFG_PDN_CON2 (MTK_CONFG_BASE + 0x308)
-#define MTK_CONFG_PDN_CON3 (MTK_CONFG_BASE + 0x30C)
-#define MTK_CONFG_PDN_SET0 (MTK_CONFG_BASE + 0x310)
-#define MTK_CONFG_PDN_SET1 (MTK_CONFG_BASE + 0x314)
-#define MTK_CONFG_PDN_SET2 (MTK_CONFG_BASE + 0x318)
-#define MTK_CONFG_PDN_SET3 (MTK_CONFG_BASE + 0x31C)
-#define MTK_CONFG_PDN_CLR0 (MTK_CONFG_BASE + 0x320)
-#define MTK_CONFG_PDN_CLR1 (MTK_CONFG_BASE + 0x324)
-#define MTK_CONFG_PDN_CLR2 (MTK_CONFG_BASE + 0x328)
-#define MTK_CONFG_PDN_CLR3 (MTK_CONFG_BASE + 0x32C)
-
-/* CONFG_MCUCLK_CON bit fields definitions */
-#define MCUCLK_CON_AHBX8CLK_SHIFT (0)
-#define MCUCLK_CON_AHBX4CLK_SHIFT (4)
-#define MCUCLK_CON_ARMCLK_SHIFT (8)
-#define MCUCLK_CON_EMICLK_SHIFT (12)
-
-/* PDN_CON0 bit fields definitions */
-#define PDN_CON0_CON0_DMA (1 << 0)
-#define PDN_CON0_USB (1 << 1)
-#define PDN_CON0_GCU (1 << 2)
-#define PDN_CON0_WAVE (1 << 3)
-#define PDN_CON0_SEJ (1 << 4)
-#define PDN_CON0_IR (1 << 6)
-#define PDN_CON0_PWM3 (1 << 7)
-#define PDN_CON0_PWM (1 << 8)
-#define PDN_CON0_SIM2 (1 << 10)
-#define PDN_CON0_IRDBG1 (1 << 12)
-#define PDN_CON0_IRDBG2 (1 << 13)
-
-/* PDN_CON1 bit fields definitions */
-#define PDN_CON1_GPT (1 << 0)
-#define PDN_CON1_KP (1 << 1)
-#define PDN_CON1_GPIO (1 << 2)
-#define PDN_CON1_UART1 (1 << 3)
-#define PDN_CON1_SIM (1 << 4)
-#define PDN_CON1_PWM1 (1 << 5)
-#define PDN_CON1_LCD (1 << 7)
-#define PDN_CON1_UART2 (1 << 8)
-#define PDN_CON1_MSDC (1 << 9)
-#define PDN_CON1_TP (1 << 10)
-#define PDN_CON1_PWM2 (1 << 11)
-#define PDN_CON1_NFI (1 << 12)
-#define PDN_CON1_UART3 (1 << 14)
-#define PDN_CON1_IRDA (1 << 15)
-
-/* PDN_CON2 bit fields definitions */
-#define PDN_CON2_TDMA (1 << 0)
-#define PDN_CON2_RTC (1 << 1)
-#define PDN_CON2_BSI (1 << 2)
-#define PDN_CON2_BPI (1 << 3)
-#define PDN_CON2_AFC (1 << 4)
-#define PDN_CON2_APC (1 << 5)
-
-/*
- * Reset Generation Unit block section
- */
-#define MTK_RGU_WDT_MODE (MTK_RGU_BASE + 0x00)
-#define MTK_RGU_WDT_LENGTH (MTK_RGU_BASE + 0x04)
-#define MTK_RGU_WDT_RESTART (MTK_RGU_BASE + 0x08)
-#define MTK_RGU_WDT_STA (MTK_RGU_BASE + 0x0C)
-#define MTK_RGU_SW_PERIPH_RSTN (MTK_RGU_BASE + 0x10)
-#define MTK_RGU_SW_DSP_RSTN (MTK_RGU_BASE + 0x14)
-#define MTK_RGU_WDT_RSTINTERVAL (MTK_RGU_BASE + 0x18)
-#define MTK_RGU_WDT_SWRST (MTK_RGU_BASE + 0x1C)
-
-#define WDT_MODE_KEY 0x2200
-#define WDT_LENGTH_KEY 0x0008
-#define WDT_RESTART_KEY 0x1971
-#define SW_PERIPH_RSTN_KEY 0x0037
-#define WDT_SWRST_KEY 0x1209
-
-/*
- * RTC block section
- */
-
-/* RTC registers definition */
-#define MTK_RTC_BBPU (MTK_RTC_BASE + 0x00)
-#define MTK_RTC_IRQ_STA (MTK_RTC_BASE + 0x04)
-#define MTK_RTC_IRQ_EN (MTK_RTC_BASE + 0x08)
-#define MTK_RTC_CII_EN (MTK_RTC_BASE + 0x0C)
-#define MTK_RTC_AL_MASK (MTK_RTC_BASE + 0x10)
-#define MTK_RTC_TC_SEC (MTK_RTC_BASE + 0x14)
-#define MTK_RTC_TC_MIN (MTK_RTC_BASE + 0x18)
-#define MTK_RTC_TC_HOU (MTK_RTC_BASE + 0x1C)
-#define MTK_RTC_TC_DOM (MTK_RTC_BASE + 0x20)
-#define MTK_RTC_TC_DOW (MTK_RTC_BASE + 0x24)
-#define MTK_RTC_TC_MTH (MTK_RTC_BASE + 0x28)
-#define MTK_RTC_TC_YEA (MTK_RTC_BASE + 0x2C)
-#define MTK_RTC_AL_SEC (MTK_RTC_BASE + 0x30)
-#define MTK_RTC_AL_MIN (MTK_RTC_BASE + 0x34)
-#define MTK_RTC_AL_HOU (MTK_RTC_BASE + 0x38)
-#define MTK_RTC_AL_DOM (MTK_RTC_BASE + 0x3C)
-#define MTK_RTC_AL_DOW (MTK_RTC_BASE + 0x40)
-#define MTK_RTC_AL_MTH (MTK_RTC_BASE + 0x44)
-#define MTK_RTC_AL_YEA (MTK_RTC_BASE + 0x48)
-#define MTK_RTC_XOSCCALI (MTK_RTC_BASE + 0x4C)
-#define MTK_RTC_POWERKEY1 (MTK_RTC_BASE + 0x50)
-#define MTK_RTC_POWERKEY2 (MTK_RTC_BASE + 0x54)
-#define MTK_RTC_PDN1 (MTK_RTC_BASE + 0x58)
-#define MTK_RTC_PDN2 (MTK_RTC_BASE + 0x5C)
-#define MTK_RTC_SPAR1 (MTK_RTC_BASE + 0x64)
-#define MTK_RTC_DIFF (MTK_RTC_BASE + 0x6C)
-#define MTK_RTC_CALI (MTK_RTC_BASE + 0x70)
-#define MTK_RTC_WRTGR (MTK_RTC_BASE + 0x74)
-
-#define POWERKEY1_MAGIC 0xA357
-#define POWERKEY2_MAGIC 0x67D2
-
-/* RTC_BBPU bit fields definitions */
-#define RTC_BBPU_PWREN (1 << 0)
-#define RTC_BBPU_WRITE_EN (1 << 1)
-#define RTC_BBPU_BBPU (1 << 2)
-#define RTC_BBPU_AUTO (1 << 3)
-#define RTC_BBPU_CLRPKY (1 << 4)
-#define RTC_BBPU_RELOAD (1 << 5)
-#define RTC_BBPU_CBUSY (1 << 6)
-#define RTC_BBPU_DBING (1 << 7)
-#define RTC_BBPU_KEY_BBPU (1 << 8)
-
-/* RTC_BBPU write is only acceptable when KEY_BBPU=0x43 */
-#define BBPU_MAGIC 0x4300
-
-/*
- * PLL block section
- */
-
-/* PLL registers definition */
-#define MTK_PLL_PLL (MTK_PLL_BASE + 0x00)
-#define MTK_PLL_PLL2 (MTK_PLL_BASE + 0x04)
-#define MTK_PLL_CLK_CON (MTK_PLL_BASE + 0x18)
-#define MTK_PLL_PDN_CON (MTK_PLL_BASE + 0x1C)
-
-/* MTK_PLL_PLL bit fields definitions */
-#define PLL_PLLVCOSEL (0 << 0)
-#define PLL_MPLLSEL_SYSCLK (1 << 3)
-#define PLL_MPLLSEL_PLL (2 << 3)
-#define PLL_DPLLSEL (1 << 5)
-#define PLL_UPLLSEL (1 << 6)
-#define PLL_RST (1 << 7)
-#define PLL_CALI (1 << 8)
-
-/* MTK_PLL_CLK_CON bit fields definitions */
-#define PLL_CLKSQ_DIV2_DSP (1 << 0)
-#define PLL_CLKSQ_DIV2_MCU (1 << 1)
-#define PLL_CLKSQ_PLD (1 << 2)
-#define PLL_SRCCLK (1 << 7)
-#define PLL_CLKSQ_TEST (1 << 15)
-
-/* MTK_PLL_PDN_CON bit fields definitions */
-#define PLL_PDN_CON_CLKSQ (1 << 11)
-#define PLL_PDN_CON_MCU_DIV2 (1 << 12)
-#define PLL_PDN_CON_PLL (1 << 13)
-#define PLL_PDN_CON_DSP_DIV2 (1 << 15)
-
-#endif
diff --git a/Src/osmocom-bb/src/target/firmware/include/mtk/tdma_timer.h b/Src/osmocom-bb/src/target/firmware/include/mtk/tdma_timer.h
deleted file mode 100644
index dec0a8a..0000000
--- a/Src/osmocom-bb/src/target/firmware/include/mtk/tdma_timer.h
+++ /dev/null
@@ -1,60 +0,0 @@
-#ifndef _MTK_TDMA_H
-#define _MTK_TDMA_H
-
-/* MTK TDMA Timer */
-
-/* MT6235 Section 11 */
-
-enum mtk_tdma_reg {
- /* Read current quarter bit count */
- TDMA_TQCNT = 0x0000,
- /* Latched Qbit counter reset position */
- TDMA_WRAP = 0x0004,
- /* Direct Qbit counter reset position */
- TDMA_WRAPIMD = 0x0008,
- /* Event latch position */
- TDMA_EVTVAL = 0x000c,
- /* DSP software control */
- TDMA_DTIRQ = 0x0010,
- /* MCU software control */
- TDMA_CTIRQ1 = 0x0014,
- TDMA_CTIRQ2 = 0x0018,
- /* AFC control */
- TDMA_AFC0 = 0x0020,
- TDMA_AFC1 = 0x0024,
- TDMA_AFC2 = 0x0028,
- TDMA_AFC3 = 0x002c,
-
- /* BSI event */
- TDMA_BSI0 = 0x00b0,
- /* BPI event */
- TDMA_BPI0 = 0x0100,
- /* Auxiliary ADC event */
- TDMA_AUXEV0 = 0x0400,
- TDMA_AUXEV1 = 0x0404,
- /* Event Control */
- TDMA_EVTENA0 = 0x0150,
- TDMA_EVTENA1 = 0x0154,
- TDMA_EVTENA2 = 0x0158,
- TDMA_EVTENA3 = 0x015c,
- TDMA_EVTENA4 = 0x0160,
- TDMA_EVTENA5 = 0x0164,
- TDMA_EVTENA6 = 0x0168,
- TDMA_EVTENA6 = 0x016c,
- TDMA_WRAPOFS = 0x0170,
- TDMA_REGBIAS = 0x0174,
- TDMA_DTXCON = 0x0180,
- TDMA_RXCON = 0x0184,
- TDMA_BDLCON = 0x0188,
- TDMA_BULCON1 = 0x018c,
- TDMA_BULCON2 = 0x0190,
- TDMA_FB_FLAG = 0x0194,
- TDMA_FB_CLRI = 0x0198,
-};
-
-#define TDMA_BSI(n) (TDMA_BSI0 + (n)*4)
-#define TDMA_BPI(n) (TDMA_BPI0 + (n)*4)
-
-
-
-#endif /* _MTK_TDMA_H */