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authorTom2011-06-17 18:21:43 +0200
committerTom2011-06-17 18:21:43 +0200
commit8abd9a968f1aaea16239b1de7d627fb54160257f (patch)
treef9e28f25a0e4561c9dd3a1d6b5ba51e6e6954d46 /Src/osmocom-bb/src/target/firmware/lib/bitops.h
parentinitial commit .. (diff)
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Initial Commit
Diffstat (limited to 'Src/osmocom-bb/src/target/firmware/lib/bitops.h')
-rw-r--r--Src/osmocom-bb/src/target/firmware/lib/bitops.h33
1 files changed, 33 insertions, 0 deletions
diff --git a/Src/osmocom-bb/src/target/firmware/lib/bitops.h b/Src/osmocom-bb/src/target/firmware/lib/bitops.h
new file mode 100644
index 0000000..428c9a6
--- /dev/null
+++ b/Src/osmocom-bb/src/target/firmware/lib/bitops.h
@@ -0,0 +1,33 @@
+ .macro bitop, instr
+ and r2, r0, #7
+ mov r3, #1
+ mov r3, r3, lsl r2
+ save_and_disable_irqs ip
+ ldrb r2, [r1, r0, lsr #3]
+ \instr r2, r2, r3
+ strb r2, [r1, r0, lsr #3]
+ restore_irqs ip
+ mov pc, lr
+ .endm
+
+/**
+ * testop - implement a test_and_xxx_bit operation.
+ * @instr: operational instruction
+ * @store: store instruction
+ *
+ * Note: we can trivially conditionalise the store instruction
+ * to avoid dirting the data cache.
+ */
+ .macro testop, instr, store
+ add r1, r1, r0, lsr #3
+ and r3, r0, #7
+ mov r0, #1
+ save_and_disable_irqs ip
+ ldrb r2, [r1]
+ tst r2, r0, lsl r3
+ \instr r2, r2, r0, lsl r3
+ \store r2, [r1]
+ restore_irqs ip
+ moveq r0, #0
+ mov pc, lr
+ .endm