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-rw-r--r--Src/osmocombb/src/target/firmware/board/common/calypso_pwl.S21
-rw-r--r--Src/osmocombb/src/target/firmware/board/common/calypso_uart.S92
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal/LINKAGE.txt12
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal/exceptions_redirect.S24
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal/exceptions_redirected.S20
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal/handlers.S79
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal/header.S11
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal/highram.lds121
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal/macros.S76
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal/ram.lds123
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal/rf_power.c62
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal/rffe_dualband.c102
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal/start.ram.S26
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal/start.rom.S32
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal_e86/init.c143
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal_e88/LINKAGE.txt33
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal_e88/MEMORY_MAP.txt21
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal_e88/flash.lds134
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal_e88/init.c136
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal_e88/loader.lds147
-rw-r--r--Src/osmocombb/src/target/firmware/board/compal_e99/init.c140
-rw-r--r--Src/osmocombb/src/target/firmware/board/gta0x/init.c136
-rw-r--r--Src/osmocombb/src/target/firmware/board/gta0x/rf_power.c63
-rw-r--r--Src/osmocombb/src/target/firmware/board/gta0x/rffe_gta0x_triband.c131
-rw-r--r--Src/osmocombb/src/target/firmware/board/manifest.c7
-rw-r--r--Src/osmocombb/src/target/firmware/board/mediatek/macros.S76
-rw-r--r--Src/osmocombb/src/target/firmware/board/mediatek/ram.lds112
-rw-r--r--Src/osmocombb/src/target/firmware/board/mediatek/start.ram.S26
-rw-r--r--Src/osmocombb/src/target/firmware/board/mediatek/uart.c424
-rw-r--r--Src/osmocombb/src/target/firmware/board/mt62xx/init.c139
-rw-r--r--Src/osmocombb/src/target/firmware/board/pirelli_dpl10/init.c127
-rw-r--r--Src/osmocombb/src/target/firmware/board/pirelli_dpl10/rf_power.c63
-rw-r--r--Src/osmocombb/src/target/firmware/board/pirelli_dpl10/rffe_dpl10_triband.c136
33 files changed, 2995 insertions, 0 deletions
diff --git a/Src/osmocombb/src/target/firmware/board/common/calypso_pwl.S b/Src/osmocombb/src/target/firmware/board/common/calypso_pwl.S
new file mode 100644
index 0000000..90e29bf
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/common/calypso_pwl.S
@@ -0,0 +1,21 @@
+
+/* Calypso PWL driver */
+
+#define ASIC_CONF_REG 0xfffef008
+#define BA_PWL 0xfffe8000
+
+.globl pwl_init
+pwl_init: ldr r1, =ASIC_CONF_REG
+ ldr r2, [r1]
+ orr r2, r2, #0x10 @ set light output to PWL
+ str r2, [r1]
+ ldr r1, =BA_PWL
+ mov r0, #1
+ strb r0, [r1, #1] @ enable clock of PWL unut
+ mov pc, lr
+
+.globl pwl_set_level
+pwl_set_level: ldr r1, =BA_PWL
+ strb r0, [r1]
+ mov pc, lr
+
diff --git a/Src/osmocombb/src/target/firmware/board/common/calypso_uart.S b/Src/osmocombb/src/target/firmware/board/common/calypso_uart.S
new file mode 100644
index 0000000..808cb05
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/common/calypso_uart.S
@@ -0,0 +1,92 @@
+/* uart routines for early assembly code */
+
+#define BA_UART_MODEM 0xFFFF5800
+
+.macro senduart, rd, rx
+ strb \rd, [\rx, #0]
+.endm
+
+.macro busyuart, rd, rx
+1001:
+ @busy waiting until THR is empty
+ ldrb \rd, [\rx, #5] @ read LSR register
+ mov \rd, \rd, lsr #6
+ tst \rd, #1
+ beq 1001b
+.endm
+
+.macro loadsp, rd
+ ldr \rd, =BA_UART_MODEM
+.endm
+
+.section .text
+
+ .align 2
+ .type phexbuf, #object
+phexbuf: .space 12
+ .size phexubf, . - phexbuf
+
+.globl phex
+phex: adr r3, phexbuf
+ mov r2, #0
+ strb r2, [r3, r1]
+1: subs r1, r1, #1
+ movmi r0, r3
+ bmi puts_asm
+ and r2, r0, #15
+ mov r0, r0, lsr #4
+ cmp r2, #10
+ addge r2, r2, #7
+ add r2, r2, #'0'
+ strb r2, [r3, r1]
+ b 1b
+
+.globl puts_asm
+puts_asm: loadsp r3
+1: ldrb r2, [r0], #1
+ teq r2, #0
+ moveq pc, lr
+2: senduart r2, r3
+ busyuart r1, r3
+ teq r2, #'\n'
+ moveq r2, #'\r'
+ beq 2b
+ teq r0, #0
+ bne 1b
+ mov pc, lr
+
+.globl putchar_asm
+putchar_asm:
+ mov r2, r0
+ mov r0, #0
+ loadsp r3
+ b 2b
+
+.globl memdump_asm
+memdump_asm: mov r12, r0
+ mov r10, lr
+ mov r11, #0
+2: mov r0, r11, lsl #2
+ add r0, r0, r12
+ mov r1, #8
+ bl phex
+ mov r0, #':'
+ bl putchar_asm
+1: mov r0, #' '
+ bl putchar_asm
+ ldr r0, [r12, r11, lsl #2]
+ mov r1, #8
+ bl phex
+ and r0, r11, #7
+ teq r0, #3
+ moveq r0, #' '
+ bleq putchar_asm
+ and r0, r11, #7
+ add r11, r11, #1
+ teq r0, #7
+ bne 1b
+ mov r0, #'\n'
+ bl putchar_asm
+ cmp r11, #64
+ blt 2b
+ mov pc, r10
diff --git a/Src/osmocombb/src/target/firmware/board/compal/LINKAGE.txt b/Src/osmocombb/src/target/firmware/board/compal/LINKAGE.txt
new file mode 100644
index 0000000..1ae06fb
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal/LINKAGE.txt
@@ -0,0 +1,12 @@
+
+We provide the following common RAM linkages for all Compal phones:
+
+(both use the Calypso ROM loader for interrupt redirect, if required)
+
+ compalram:
+ Image for the Compal ramloader. Starts at a weird address and
+ contains various ramloader specifics.
+
+ highram:
+ Image linked to 0x820000, used for various special purposes.
+ This image is completely independent of the compal loader.
diff --git a/Src/osmocombb/src/target/firmware/board/compal/exceptions_redirect.S b/Src/osmocombb/src/target/firmware/board/compal/exceptions_redirect.S
new file mode 100644
index 0000000..a216e60
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal/exceptions_redirect.S
@@ -0,0 +1,24 @@
+
+.section .text.exceptions
+_undef_instr:
+ ldr pc, _vec_undef_instr
+_sw_interr:
+ ldr pc, _vec_sw_interr
+_prefetch_abort:
+ ldr pc, _vec_prefetch_abort
+_data_abort:
+ ldr pc, _vec_data_abort
+_reserved:
+ ldr pc, _vec_reserved
+_irq:
+ ldr pc, _vec_irq
+_fiq:
+ ldr pc, _vec_fiq
+
+_vec_undef_instr: .word(0x80001c)
+_vec_sw_interr: .word(0x800020)
+_vec_prefetch_abort: .word(0x800024)
+_vec_data_abort: .word(0x800028)
+_vec_reserved: .word(0x80002c)
+_vec_irq: .word(0x800030)
+_vec_fiq: .word(0x800034)
diff --git a/Src/osmocombb/src/target/firmware/board/compal/exceptions_redirected.S b/Src/osmocombb/src/target/firmware/board/compal/exceptions_redirected.S
new file mode 100644
index 0000000..6908396
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal/exceptions_redirected.S
@@ -0,0 +1,20 @@
+
+/* Exception Vectors like they are needed for the exception vector
+ indirection of the internal boot ROM. The following section must be liked
+ to appear at 0x80001c */
+.section .text.exceptions
+_undef_instr:
+ b handle_abort
+_sw_interr:
+ b _sw_interr
+_prefetch_abort:
+ b handle_abort
+_data_abort:
+ b handle_abort
+_reserved:
+ b _reserved
+_irq:
+ b irq_entry
+_fiq:
+ b fiq_entry
+
diff --git a/Src/osmocombb/src/target/firmware/board/compal/handlers.S b/Src/osmocombb/src/target/firmware/board/compal/handlers.S
new file mode 100644
index 0000000..ef044e3
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal/handlers.S
@@ -0,0 +1,79 @@
+
+ .EQU I_BIT, 0x80
+ .EQU F_BIT, 0x40
+
+.section .text
+
+/* handler for all kinds of aborts */
+.global handle_abort
+handle_abort:
+ @ print the PC we would jump back to...
+ sub lr, lr, #4 @ we assume to be ARM32
+
+ mov r0, lr
+ mov r1, #8
+ bl phex
+
+ @ print abort message
+ mov r0, #'A'
+ bl putchar_asm
+ mov r0, #'B'
+ bl putchar_asm
+ mov r0, #'O'
+ bl putchar_asm
+ mov r0, #'R'
+ bl putchar_asm
+ mov r0, #'T'
+ bl putchar_asm
+
+ @ disable IRQ and FIQ
+ msr CPSR_c, #I_BIT | F_BIT
+
+0: @ dead
+ b 0b
+
+/* entry point for IRQs */
+.global irq_entry
+irq_entry:
+ /* Adjust and save LR_irq in IRQ stack */
+ sub lr, lr, #4
+ stmfd sp!, {lr}
+
+ /* Save SPSR for nested interrupt */
+ mrs r14, SPSR
+ stmfd sp!, {r14}
+
+ /* Call the interrupt handler C function */
+ stmfd sp!, {r0-r4, r12}
+ bl irq
+ ldmfd sp!, {r0-r4, r12}
+
+ /* Restore SPSR_irq from IRQ stack */
+ ldmia sp!, {r14}
+ msr SPSR_cxsf, r14
+
+ /* Restore adjusted LR_irq from IRQ stack directly in the PC */
+ ldmia sp!, {pc}^
+
+/* entry point for FIQs */
+.global fiq_entry
+fiq_entry:
+ /* Adjust and save LR_irq in IRQ stack */
+ sub lr, lr, #4
+ stmfd sp!, {lr}
+
+ /* Save SPSR for nested interrupt */
+ mrs r14, SPSR
+ stmfd sp!, {r14}
+
+ /* Call the interrupt handler C function */
+ stmfd sp!, {r0-r4, r12}
+ bl fiq
+ ldmfd sp!, {r0-r4, r12}
+
+ /* Restore SPSR_irq from IRQ stack */
+ ldmia sp!, {r14}
+ msr SPSR_cxsf, r14
+
+ /* Restore adjusted LR_irq from IRQ stack directly in the PC */
+ ldmia sp!, {pc}^
diff --git a/Src/osmocombb/src/target/firmware/board/compal/header.S b/Src/osmocombb/src/target/firmware/board/compal/header.S
new file mode 100644
index 0000000..747f680
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal/header.S
@@ -0,0 +1,11 @@
+/*
+ * This is a textual header that is prepended to images where appropriate.
+ *
+ * It is meant to ease identification of our firmwares in dumps as well
+ * as filling some space that is used for the same purpose by the vendor.
+ *
+ */
+.section .compal.header
+.ascii "OSMOCOM"
+. = 0x20
+.ascii GIT_REVISION
diff --git a/Src/osmocombb/src/target/firmware/board/compal/highram.lds b/Src/osmocombb/src/target/firmware/board/compal/highram.lds
new file mode 100644
index 0000000..1f0a5a6
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal/highram.lds
@@ -0,0 +1,121 @@
+/*
+ * Linker script for running from upper internal RAM on the TI Calypso
+ *
+ * This script creates a binary that can be loaded into high ram on
+ * all Calypso devices. It can be jumped into directly at the load
+ * address.
+ *
+ * This is used for debugging the loader and for general hacking purposes.
+ *
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+MEMORY
+{
+ /* lowram: could be anything, we place exception vectors here */
+ XRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x00020000
+ /* highram binary: our text, initialized data */
+ LRAM (rw) : ORIGIN = 0x00820000, LENGTH = 0x00010000
+ /* highram binary: our unitialized data, stacks, heap */
+ IRAM (rw) : ORIGIN = 0x00830000, LENGTH = 0x00010000
+}
+SECTIONS
+{
+ . = 0x820000;
+
+ /* initialization code */
+ .text.start : {
+ PROVIDE(_start = .);
+ KEEP(*(.text.start))
+ *(.text.start)
+ } > LRAM
+
+ /* exception vectors linked for 0x80001c to 0x800034 */
+ .text.exceptions 0x80001c : AT (LOADADDR(.text.start) + SIZEOF(.text.start)) {
+ KEEP(*(.text.exceptions))
+ * (.text.exceptions)
+ . = ALIGN(4);
+ } > XRAM
+ PROVIDE(_exceptions = LOADADDR(.text.exceptions));
+
+ /* code */
+ . = ALIGN(4);
+ .text (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) :
+ AT (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) {
+ /* regular code */
+ *(.text*)
+ /* always-in-ram code */
+ *(.ramtext*)
+ /* gcc voodoo */
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)
+ . = ALIGN(4);
+ } > LRAM
+ PROVIDE(_text_start = LOADADDR(.text));
+ PROVIDE(_text_end = LOADADDR(.text) + SIZEOF(.text));
+
+ /* constructor pointers */
+ .ctors : {
+ /* ctor count */
+ LONG(SIZEOF(.ctors) / 4 - 2)
+ /* ctor pointers */
+ KEEP(*(SORT(.ctors)))
+ /* end of list */
+ LONG(0)
+ } > LRAM
+ PROVIDE(_ctor_start = LOADADDR(.ctors));
+ PROVIDE(_ctor_end = LOADADDR(.ctors) + SIZEOF(.ctors));
+
+ /* destructor pointers */
+ .dtors : {
+ /* dtor count */
+ LONG(SIZEOF(.dtors) / 4 - 2)
+ /* dtor pointers */
+ KEEP(*(SORT(.dtors)))
+ /* end of list */
+ LONG(0)
+ } > LRAM
+ PROVIDE(_dtor_start = LOADADDR(.dtors));
+ PROVIDE(_dtor_end = LOADADDR(.dtors) + SIZEOF(.dtors));
+
+ /* read-only data */
+ . = ALIGN(4);
+ .rodata : {
+ *(.rodata*)
+ } > LRAM
+ PROVIDE(_rodata_start = LOADADDR(.rodata));
+ PROVIDE(_rodata_end = LOADADDR(.rodata) + SIZEOF(.rodata));
+
+ /* initialized data */
+ . = ALIGN(4);
+ .data : {
+ *(.data)
+ } > LRAM
+ PROVIDE(_data_start = LOADADDR(.data));
+ PROVIDE(_data_end = LOADADDR(.data) + SIZEOF(.data));
+
+ /* pic offset tables */
+ . = ALIGN(4);
+ .got : {
+ *(.got)
+ *(.got.plt) *(.igot.plt) *(.got) *(.igot)
+ } > LRAM
+ PROVIDE(_got_start = LOADADDR(.got));
+ PROVIDE(_got_end = LOADADDR(.got) + SIZEOF(.got));
+
+ /* uninitialized data */
+ .bss (NOLOAD) : {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss)
+ } > IRAM
+ . = ALIGN(4);
+ __bss_end = .;
+ PROVIDE(_bss_start = __bss_start);
+ PROVIDE(_bss_end = __bss_end);
+
+ /* end of image */
+ . = ALIGN(4);
+ _end = .;
+ PROVIDE(end = .);
+}
diff --git a/Src/osmocombb/src/target/firmware/board/compal/macros.S b/Src/osmocombb/src/target/firmware/board/compal/macros.S
new file mode 100644
index 0000000..613e6bd
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal/macros.S
@@ -0,0 +1,76 @@
+
+.macro clear_bss
+ mov r0, #0
+ ldr r1, =__bss_start
+ ldr r2, =__bss_end
+loop_bss:
+ cmp r1, r2
+ strlo r0, [r1], #4
+ blo loop_bss
+.endm
+
+.macro copy_data
+ ldr r0, =__data_start
+ ldr r1, =_data_start
+ ldr r2, =__data_end
+ cmp r0, r2
+ beq done_data
+loop_data:
+ ldrb r4, [r0], #1
+ strb r4, [r1], #1
+ cmp r0, r2
+ bne loop_data
+done_data:
+.endm
+
+.macro copy_ramtext
+ ldr r0, =__ramtext_start
+ ldr r1, =_ramtext_start
+ ldr r2, =__ramtext_end
+ cmp r0, r2
+ beq done_ramtext
+loop_ramtext:
+ ldrb r4, [r0], #1
+ strb r4, [r1], #1
+ cmp r0, r2
+ bne loop_ramtext
+done_ramtext:
+.endm
+
+ .EQU ARM_MODE_FIQ, 0x11
+ .EQU ARM_MODE_IRQ, 0x12
+ .EQU ARM_MODE_SVC, 0x13
+
+ .EQU I_BIT, 0x80
+ .EQU F_BIT, 0x40
+
+#define TOP_OF_RAM 0x083fff0
+#define FIQ_STACK_SIZE 1024
+#define IRQ_STACK_SIZE 1024
+
+.macro init_stacks
+ /* initialize stacks, starting at TOP_OF_RAM */
+ ldr r0, =TOP_OF_RAM
+
+ /* initialize FIQ stack */
+ msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
+ mov r13, r0
+ sub r0, r0, #FIQ_STACK_SIZE
+
+ /* initialize IRQ stack */
+ msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
+ mov r13, r0
+ sub r0, r0, #IRQ_STACK_SIZE
+
+ /* initialize supervisor stack */
+ msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT
+ mov r13, r0
+.endm
+
+.macro call_ctors
+ /* call constructor functions */
+ ldr r0, =_ctor_start
+ ldr r1, =_ctor_end
+ bl do_global_ctors
+.endm
+
diff --git a/Src/osmocombb/src/target/firmware/board/compal/ram.lds b/Src/osmocombb/src/target/firmware/board/compal/ram.lds
new file mode 100644
index 0000000..342870d
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal/ram.lds
@@ -0,0 +1,123 @@
+/*
+ * Linker script for running from internal SRAM on Compal phones
+ *
+ * This script is tailored specifically to the requirements imposed
+ * on us by the Compal bootloader.
+ *
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+MEMORY
+{
+ /* compal-loaded binary: our text, initialized data */
+ LRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x00010000
+ /* compal-loaded binary: our unitialized data, stacks, heap */
+ IRAM (rw) : ORIGIN = 0x00810000, LENGTH = 0x00010000
+}
+SECTIONS
+{
+ . = 0x800000;
+
+ /* romloader data section, contains passthru interrupt vectors */
+ .compal.loader (NOLOAD) : { . = 0x100; } > LRAM
+
+ /* image signature (prepended by osmocon according to phone type) */
+ .compal.header (NOLOAD) : { . = 4; } > LRAM
+
+ /* initialization code */
+ . = ALIGN(4);
+ .text.start : {
+ PROVIDE(_start = .);
+ KEEP(*(.text.start))
+ *(.text.start)
+ } > LRAM
+
+ /* exception vectors from 0x80001c to 0x800034 */
+ .text.exceptions 0x80001c : AT (LOADADDR(.text.start) + SIZEOF(.text.start)) {
+ KEEP(*(.text.exceptions))
+ * (.text.exceptions)
+ . = ALIGN(4);
+ } > LRAM
+ PROVIDE(_exceptions = LOADADDR(.text.exceptions));
+
+ /* code */
+ . = ALIGN(4);
+ .text (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) :
+ AT (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) {
+ /* regular code */
+ *(.text*)
+ /* always-in-ram code */
+ *(.ramtext*)
+ /* gcc voodoo */
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)
+ . = ALIGN(4);
+ } > LRAM
+ PROVIDE(_text_start = LOADADDR(.text));
+ PROVIDE(_text_end = LOADADDR(.text) + SIZEOF(.text));
+
+ /* constructor pointers */
+ .ctors : {
+ /* ctor count */
+ LONG(SIZEOF(.ctors) / 4 - 2)
+ /* ctor pointers */
+ KEEP(*(SORT(.ctors)))
+ /* end of list */
+ LONG(0)
+ } > LRAM
+ PROVIDE(_ctor_start = LOADADDR(.ctors));
+ PROVIDE(_ctor_end = LOADADDR(.ctors) + SIZEOF(.ctors));
+
+ /* destructor pointers */
+ .dtors : {
+ /* dtor count */
+ LONG(SIZEOF(.dtors) / 4 - 2)
+ /* dtor pointers */
+ KEEP(*(SORT(.dtors)))
+ /* end of list */
+ LONG(0)
+ } > LRAM
+ PROVIDE(_dtor_start = LOADADDR(.dtors));
+ PROVIDE(_dtor_end = LOADADDR(.dtors) + SIZEOF(.dtors));
+
+ /* read-only data */
+ . = ALIGN(4);
+ .rodata : {
+ *(.rodata*)
+ } > LRAM
+ PROVIDE(_rodata_start = LOADADDR(.rodata));
+ PROVIDE(_rodata_end = LOADADDR(.rodata) + SIZEOF(.rodata));
+
+ /* initialized data */
+ . = ALIGN(4);
+ .data : {
+ *(.data)
+ } > LRAM
+ PROVIDE(_data_start = LOADADDR(.data));
+ PROVIDE(_data_end = LOADADDR(.data) + SIZEOF(.data));
+
+ /* pic offset tables */
+ . = ALIGN(4);
+ .got : {
+ *(.got)
+ *(.got.plt) *(.igot.plt) *(.got) *(.igot)
+ } > LRAM
+ PROVIDE(_got_start = LOADADDR(.got));
+ PROVIDE(_got_end = LOADADDR(.got) + SIZEOF(.got));
+
+ /* uninitialized data */
+ .bss (NOLOAD) : {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss)
+ } > IRAM
+ . = ALIGN(4);
+ __bss_end = .;
+ PROVIDE(_bss_start = __bss_start);
+ PROVIDE(_bss_end = __bss_end);
+
+ /* end of image */
+ . = ALIGN(4);
+ _end = .;
+ PROVIDE(end = .);
+}
diff --git a/Src/osmocombb/src/target/firmware/board/compal/rf_power.c b/Src/osmocombb/src/target/firmware/board/compal/rf_power.c
new file mode 100644
index 0000000..fbbe65a
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal/rf_power.c
@@ -0,0 +1,62 @@
+/* Tx RF power calibration for the Compal/Motorola dualband phones */
+
+/* (C) 2010 by Harald Welte <laforge@gnumonks.org>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <stdint.h>
+#include <osmocom/core/utils.h>
+
+/* GSM900 ARFCN 33, Measurements by Steve Markgraf / May 2010 */
+const int16_t dbm2apc_gsm900[] = {
+ [0] = 151,
+ [1] = 152,
+ [2] = 153,
+ [3] = 155,
+ [4] = 156,
+ [5] = 158,
+ [6] = 160,
+ [7] = 162,
+ [8] = 164,
+ [9] = 167,
+ [10] = 170,
+ [11] = 173,
+ [12] = 177,
+ [13] = 182,
+ [14] = 187,
+ [15] = 192,
+ [16] = 199,
+ [17] = 206,
+ [18] = 214,
+ [19] = 223,
+ [20] = 233,
+ [21] = 244,
+ [22] = 260,
+ [23] = 271,
+ [24] = 288,
+ [25] = 307,
+ [26] = 327,
+ [27] = 350,
+ [28] = 376,
+ [29] = 407,
+ [30] = 456,
+ [31] = 575,
+};
+
+const int dbm2apc_gsm900_max = ARRAY_SIZE(dbm2apc_gsm900) - 1;
diff --git a/Src/osmocombb/src/target/firmware/board/compal/rffe_dualband.c b/Src/osmocombb/src/target/firmware/board/compal/rffe_dualband.c
new file mode 100644
index 0000000..f4b7361
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal/rffe_dualband.c
@@ -0,0 +1,102 @@
+#include <stdint.h>
+#include <stdio.h>
+
+#include <debug.h>
+#include <memory.h>
+#include <rffe.h>
+#include <calypso/tsp.h>
+#include <rf/trf6151.h>
+
+/* This is a value that has been measured on the C123 by Harald: 71dBm,
+ it is the difference between the input level at the antenna and what
+ the DSP reports, subtracted by the total gain of the TRF6151 */
+#define SYSTEM_INHERENT_GAIN 71
+
+/* describe how the RF frontend is wired on the Motorola E88 board (C117/C118/C121/C123) */
+
+#define RITA_RESET TSPACT(0) /* Reset of the Rita TRF6151 */
+#define PA_ENABLE TSPACT(1) /* Enable the Power Amplifier */
+#define TRENA TSPACT(6) /* Transmit Enable (Antenna Switch) */
+#define GSM_TXEN TSPACT(8) /* GSM (as opposed to DCS) Transmit */
+
+#define IOTA_STROBE TSPEN(0) /* Strobe for the Iota TSP */
+#define RITA_STROBE TSPEN(2) /* Strobe for the Rita TSP */
+
+/* switch RF Frontend Mode */
+void rffe_mode(enum gsm_band band, int tx)
+{
+ uint16_t tspact = tsp_act_state();
+
+ /* First we mask off all bits from the state cache */
+ tspact &= ~PA_ENABLE;
+ tspact |= TRENA | GSM_TXEN; /* low-active */
+
+#ifdef CONFIG_TX_ENABLE
+ /* Then we selectively set the bits on, if required */
+ if (tx) {
+ tspact &= ~TRENA;
+ if (band == GSM_BAND_850 || band == GSM_BAND_900)
+ tspact &= ~GSM_TXEN;
+ tspact |= PA_ENABLE;
+ }
+#endif /* TRANSMIT_SUPPORT */
+
+ tsp_act_update(tspact);
+}
+
+/* Returns RF wiring */
+uint32_t rffe_get_rx_ports(void)
+{
+ return (1 << PORT_LO) | (1 << PORT_DCS1800);
+}
+
+uint32_t rffe_get_tx_ports(void)
+{
+ return (1 << PORT_LO) | (1 << PORT_HI);
+}
+
+
+#define MCU_SW_TRACE 0xfffef00e
+#define ARM_CONF_REG 0xfffef006
+
+void rffe_init(void)
+{
+ uint16_t reg;
+
+ reg = readw(ARM_CONF_REG);
+ reg &= ~ (1 << 5); /* TSPACT6 I/O function, not nCS6 */
+ writew(reg, ARM_CONF_REG);
+
+ reg = readw(MCU_SW_TRACE);
+ reg &= ~(1 << 5); /* TSPACT8 I/O function, not nMREQ */
+ writew(reg, MCU_SW_TRACE);
+
+ /* Configure the TSPEN which is connected to the TWL3025 */
+ tsp_setup(IOTA_STROBE, 1, 0, 0);
+
+ trf6151_init(RITA_STROBE, RITA_RESET);
+}
+
+uint8_t rffe_get_gain(void)
+{
+ return trf6151_get_gain();
+}
+
+void rffe_set_gain(uint8_t dbm)
+{
+ trf6151_set_gain(dbm);
+}
+
+const uint8_t system_inherent_gain = SYSTEM_INHERENT_GAIN;
+
+/* Given the expected input level of exp_inp dBm/8 and the target of target_bb
+ * dBm8, configure the RF Frontend with the respective gain */
+void rffe_compute_gain(int16_t exp_inp, int16_t target_bb)
+{
+ trf6151_compute_gain(exp_inp, target_bb);
+}
+
+void rffe_rx_win_ctrl(int16_t exp_inp, int16_t target_bb)
+{
+ /* FIXME */
+}
diff --git a/Src/osmocombb/src/target/firmware/board/compal/start.ram.S b/Src/osmocombb/src/target/firmware/board/compal/start.ram.S
new file mode 100644
index 0000000..c8f242c
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal/start.ram.S
@@ -0,0 +1,26 @@
+
+.section .text.start
+
+#include "macros.S"
+
+.globl _start
+_start:
+ /* clear bss section */
+ clear_bss
+
+ /* initialize all stacks */
+ init_stacks
+
+ /* call constructors */
+ call_ctors
+
+ /* jump to main */
+ ldr pc, _jump_main
+
+ /* endless loop at end of program */
+_loop:
+ b _loop
+ b _start
+
+_jump_main:
+ .word main
diff --git a/Src/osmocombb/src/target/firmware/board/compal/start.rom.S b/Src/osmocombb/src/target/firmware/board/compal/start.rom.S
new file mode 100644
index 0000000..211bea8
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal/start.rom.S
@@ -0,0 +1,32 @@
+
+.section .text.start
+
+#include "macros.S"
+
+.globl _start
+_start:
+ /* clear bss section */
+ clear_bss
+
+ /* copy data to ram */
+ copy_data
+
+ /* copy alway-in-ram code */
+ copy_ramtext
+
+ /* initialize all stacks */
+ init_stacks
+
+ /* call constructors */
+ call_ctors
+
+ /* jump to main */
+ ldr pc, _jump_main
+
+ /* endless loop at end of program */
+_loop:
+ b _loop
+ b _start
+
+_jump_main:
+ .word main
diff --git a/Src/osmocombb/src/target/firmware/board/compal_e86/init.c b/Src/osmocombb/src/target/firmware/board/compal_e86/init.c
new file mode 100644
index 0000000..1de6193
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal_e86/init.c
@@ -0,0 +1,143 @@
+/* Initialization for the Compal E86 (Motorola C139/C140) */
+
+/* (C) 2010 by Harald Welte <laforge@gnumonks.org>
+ * (C) 2010 by Steve Markgraf <steve@steve-m.de>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include <debug.h>
+#include <ctors.h>
+#include <memory.h>
+#include <board.h>
+#include <keypad.h>
+#include <console.h>
+#include <flash/cfi_flash.h>
+
+#include <calypso/irq.h>
+#include <calypso/clock.h>
+#include <calypso/dma.h>
+#include <calypso/rtc.h>
+#include <calypso/timer.h>
+#include <uart.h>
+#include <calypso/backlight.h>
+
+#include <comm/sercomm.h>
+
+#include <abb/twl3025.h>
+#include <rf/trf6151.h>
+#include <display.h>
+
+#define ARMIO_LATCH_OUT 0xfffe4802
+#define IO_CNTL_REG 0xfffe4804
+#define ASIC_CONF_REG 0xfffef008
+
+static void board_io_init(void)
+{
+ uint16_t reg;
+
+ reg = readw(ASIC_CONF_REG);
+ /* LCD Set I/O(3) / SA0 to I/O(3) mode */
+ reg &= ~( (1 << 12) | (1 << 10) | (1 << 7) | (1 << 1)) ;
+ /* don't set function pins to I2C Mode, C155 uses UWire */
+ /* TWL3025: Set SPI+RIF RX clock to rising edge */
+ reg |= (1 << 13) | (1 << 14);
+ writew(reg, ASIC_CONF_REG);
+
+ /* LCD Set I/O(3) to output mode and enable C140 backlight (IO1) */
+ /* FIXME: Put the display backlight control to backlight.c */
+ reg = readw(IO_CNTL_REG);
+ reg &= ~((1 << 3) | (1 << 1));
+ writew(reg, IO_CNTL_REG);
+
+ /* LCD Set I/O(3) output low */
+ reg = readw(ARMIO_LATCH_OUT);
+ reg &= ~(1 << 3);
+ reg |= (1 << 1);
+ writew(reg, ARMIO_LATCH_OUT);
+}
+
+void board_init(void)
+{
+ /* Disable watchdog (compal loader leaves it enabled) */
+ wdog_enable(0);
+
+ /* Configure memory interface */
+ calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS2, 5, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS3, 5, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_CS4, 0, CALYPSO_MEM_8bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS6, 0, CALYPSO_MEM_32bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS7, 0, CALYPSO_MEM_32bit, 0);
+
+ /* Set VTCXO_DIV2 = 1, configure PLL for 104 MHz and give ARM half of that */
+ calypso_clock_set(2, CALYPSO_PLL13_104_MHZ, ARM_MCLK_DIV_2);
+
+ /* Configure the RHEA bridge with some sane default values */
+ calypso_rhea_cfg(0, 0, 0xff, 0, 1, 0, 0);
+
+ /* Initialize board-specific GPIO */
+ board_io_init();
+
+ /* Enable bootrom mapping to route exception vectors to RAM */
+ calypso_bootrom(1);
+ calypso_exceptions_install();
+
+ /* Initialize interrupt controller */
+ irq_init();
+
+ /* initialize MODEM UART to be used for sercomm*/
+ uart_init(SERCOMM_UART_NR, 1);
+ uart_baudrate(SERCOMM_UART_NR, UART_115200);
+
+ /* initialize IRDA UART to be used for old-school console code.
+ * note: IRDA uart only accessible on C115 and C117 PCB */
+ uart_init(CONS_UART_NR, 1);
+ uart_baudrate(CONS_UART_NR, UART_115200);
+
+ /* Initialize hardware timers */
+ hwtimer_init();
+
+ /* Initialize DMA controller */
+ dma_init();
+
+ /* Initialize real time clock */
+ rtc_init();
+
+ /* Initialize system timers (uses hwtimer 2) */
+ timer_init();
+
+ /* Initialize LCD driver (uses UWire) */
+ display = &td014_display;
+ display_init();
+ bl_mode_pwl(1);
+ bl_level(0);
+
+ /* Initialize keypad driver */
+ keypad_init(1);
+
+ /* Initialize ABB driver (uses SPI) */
+ twl3025_init();
+
+ /* enable LEDB driver of Iota for keypad backlight */
+ twl3025_reg_write(AUXLED, 0x02);
+}
diff --git a/Src/osmocombb/src/target/firmware/board/compal_e88/LINKAGE.txt b/Src/osmocombb/src/target/firmware/board/compal_e88/LINKAGE.txt
new file mode 100644
index 0000000..8adaf86
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal_e88/LINKAGE.txt
@@ -0,0 +1,33 @@
+
+The Compal E88 supports the common Compal RAM linkages.
+These operate entirely from the Calypso internal RAM.
+
+Flash linkages are structured as follows:
+
+ e88loader:
+ Linked at address of original compal application (0x2000).
+ Provides interrupt vectors as expected by compal loader.
+ Allows interrupt redirection (XXX to where?).
+
+ We introduce this for the following reasons:
+ 1. We want to start our app at 0x10000, because that
+ is the first flash page after the loader page, allowing
+ us a higher degree of "unbrickability" by never reflashing
+ the bootloader.
+ 2. We want to keep the compal loader so we do not need even
+ more boot options and to allow recovery of original firmware.
+ 3. When there is a custom app in flash at 0xFFFF, just turning
+ the phone on with the compal loader would jump into an incomplete
+ motorola app. That might not even allow turning the phone off.
+ The loader provides this functionality.
+ 4. We do not want to patch the compal loader for interrupt
+ redirect and entry vectors. So we need to place something between
+ 0x2000 and 0x10000 anyway. And since there is space, why not put
+ the whole loader in there.
+ 5. This loader has a good chance of being able to read crash buffers.
+ and examining RAM without it being clobbered by a ram upload.
+
+ e88flash:
+ Our main application linkage, starting at 0x10000 and going through
+ all of flash. Data storage locations are still to be determined.
+
diff --git a/Src/osmocombb/src/target/firmware/board/compal_e88/MEMORY_MAP.txt b/Src/osmocombb/src/target/firmware/board/compal_e88/MEMORY_MAP.txt
new file mode 100644
index 0000000..6094aa9
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal_e88/MEMORY_MAP.txt
@@ -0,0 +1,21 @@
+The Compal E88 has the following physical memory map:
+
+ /* 2 MBytes of external flash memory */
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x200000
+ /* 256 kBytes of internal zero-waitstate sram */
+ IRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x040000
+ /* 256 kBytes of external slow sram */
+ ERAM (rw) : ORIGIN = 0x01000000, LENGTH = 0x040000
+
+The flash layout, as distributed, is:
+
+ 0x00000000 0x2000 Compal loader
+ 0x00002000 >>>>>> Compal application and storage
+
+Our flash layout is:
+
+ 0x00000000 0x2000 Compal loader
+ 0x00002000 0xE000 OSMOCOM loader (see LINKAGE.txt for reasoning)
+ 0x00010000 >>>>>> OSMOCOM application and storage
+
+(XXX: determine storage location / storage descriptor location)
diff --git a/Src/osmocombb/src/target/firmware/board/compal_e88/flash.lds b/Src/osmocombb/src/target/firmware/board/compal_e88/flash.lds
new file mode 100644
index 0000000..cf0f6a4
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal_e88/flash.lds
@@ -0,0 +1,134 @@
+/*
+ * Linker script for flashed applications on the Compal E88
+ *
+ * This script creates a binary that can be linked at 0xFFFF, starting
+ * with the second flash page. This is what a phone application or
+ * pure layer1 device uses.
+ *
+ * XXX: interrupts?
+ *
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+MEMORY
+{
+ LOADR (rx) : ORIGIN = 0x00000000, LENGTH = 0x10000
+ /* 2 MBytes of external flash memory (minus loader) */
+ FLASH (rx) : ORIGIN = 0x00010000, LENGTH = 0x1F0000
+ /* 256 kBytes of internal zero-waitstate sram */
+ IRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x040000
+ /* 256 kBytes of external slow sram */
+ ERAM (rw) : ORIGIN = 0x01000000, LENGTH = 0x040000
+}
+SECTIONS
+{
+ /* entrypoint */
+ .text.start : {
+ PROVIDE(_start = .);
+ KEEP(*(.text.start))
+ *(.text.start)
+ } > FLASH
+
+ /* exception vectors from 0x80001c to 0x800034 */
+ .text.exceptions 0x80001c : {
+ KEEP(*(.text.exceptions))
+ * (.text.exceptions)
+ . = ALIGN(4);
+ } > IRAM AT> FLASH
+ PROVIDE(_exceptions = LOADADDR(.text.exceptions));
+
+ /* code */
+ .text : {
+ /* regular code */
+ *(.text*)
+ /* gcc voodoo */
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)
+ } > FLASH
+ PROVIDE(_text_start = ADDR(.text));
+ PROVIDE(_text_end = ADDR(.text) + SIZEOF(.text));
+
+ /* constructor pointers */
+ .ctors : {
+ /* ctor count */
+ LONG(SIZEOF(.ctors) / 4 - 2)
+ /* ctor pointers */
+ KEEP(*(SORT(.ctors)))
+ /* end of list */
+ LONG(0)
+ } > FLASH
+ PROVIDE(_ctor_start = LOADADDR(.ctors));
+ PROVIDE(_ctor_end = LOADADDR(.ctors) + SIZEOF(.ctors));
+
+ /* destructor pointers */
+ .dtors : {
+ /* dtor count */
+ LONG(SIZEOF(.dtors) / 4 - 2)
+ /* dtor pointers */
+ KEEP(*(SORT(.dtors)))
+ /* end of list */
+ LONG(0)
+ } > FLASH
+ PROVIDE(_dtor_start = LOADADDR(.dtors));
+ PROVIDE(_dtor_end = LOADADDR(.dtors) + SIZEOF(.dtors));
+
+ /* read-only data */
+ .rodata : {
+ *(.rodata*)
+ } > FLASH
+ PROVIDE(_rodata_start = ADDR(.rodata));
+ PROVIDE(_rodata_end = ADDR(.rodata) + SIZEOF(.rodata));
+
+ /* pic offset tables */
+ .got : {
+ . = ALIGN(4);
+ *(.got)
+ *(.got.plt) *(.igot.plt) *(.got) *(.igot)
+ . = ALIGN(4);
+ } > FLASH
+ PROVIDE(_got_start = ADDR(.got));
+ PROVIDE(_got_end = ADDR(.got) + SIZEOF(.got));
+
+ /* reserved ram */
+ .compal.reservedram 0x800000 (NOLOAD) : {
+ . = 0xff;
+ } > IRAM
+
+ /* initialized data */
+ .data : AT (LOADADDR(.got) + SIZEOF(.got)) {
+ . = ALIGN(4);
+ *(.data)
+ . = ALIGN(4);
+ } > IRAM
+ PROVIDE(__data_start = LOADADDR(.data));
+ PROVIDE(__data_end = LOADADDR(.data) + SIZEOF(.data));
+ PROVIDE(_data_start = ADDR(.data));
+ PROVIDE(_data_end = ADDR(.data) + SIZEOF(.data));
+
+ /* ram code */
+ .ramtext : AT (LOADADDR(.data) + SIZEOF(.data)) {
+ . = ALIGN(4);
+ *(.ramtext)
+ . = ALIGN(4);
+ } > IRAM
+ PROVIDE(__ramtext_start = LOADADDR(.ramtext));
+ PROVIDE(__ramtext_end = LOADADDR(.ramtext) + SIZEOF(.ramtext));
+ PROVIDE(_ramtext_start = ADDR(.ramtext));
+ PROVIDE(_ramtext_end = ADDR(.ramtext) + SIZEOF(.ramtext));
+
+ /* uninitialized data */
+ .bss (NOLOAD) : {
+ . = ALIGN(4);
+ *(.bss)
+ . = ALIGN(4);
+ } > IRAM
+ PROVIDE(__bss_start = ADDR(.bss));
+ PROVIDE(__bss_end = ADDR(.bss) + SIZEOF(.bss));
+ PROVIDE(_bss_start = __bss_start);
+ PROVIDE(_bss_end = __bss_end);
+
+ /* end of image */
+ . = ALIGN(4);
+ _end = .;
+ PROVIDE(end = .);
+}
diff --git a/Src/osmocombb/src/target/firmware/board/compal_e88/init.c b/Src/osmocombb/src/target/firmware/board/compal_e88/init.c
new file mode 100644
index 0000000..a5bf880
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal_e88/init.c
@@ -0,0 +1,136 @@
+/* Initialization for the Compal E88 (Motorola C115...C123) */
+
+/* (C) 2010 by Harald Welte <laforge@gnumonks.org>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include <debug.h>
+#include <ctors.h>
+#include <memory.h>
+#include <board.h>
+#include <keypad.h>
+#include <console.h>
+#include <flash/cfi_flash.h>
+
+#include <calypso/irq.h>
+#include <calypso/clock.h>
+#include <calypso/dma.h>
+#include <calypso/rtc.h>
+#include <calypso/timer.h>
+#include <uart.h>
+#include <calypso/backlight.h>
+
+#include <comm/sercomm.h>
+#include <comm/timer.h>
+
+#include <abb/twl3025.h>
+#include <rf/trf6151.h>
+#include <display.h>
+
+#define ARMIO_LATCH_OUT 0xfffe4802
+#define IO_CNTL_REG 0xfffe4804
+#define ASIC_CONF_REG 0xfffef008
+
+static void board_io_init(void)
+{
+ uint16_t reg;
+
+ reg = readw(ASIC_CONF_REG);
+ /* LCD Set I/O(3) / SA0 to I/O(3) mode */
+ reg &= ~(1 << 10);
+ /* Set function pins to I2C Mode */
+ reg |= ((1 << 12) | (1 << 7)); /* SCL / SDA */
+ /* TWL3025: Set SPI+RIF RX clock to rising edge */
+ reg |= (1 << 13) | (1 << 14);
+ writew(reg, ASIC_CONF_REG);
+
+ /* LCD Set I/O(3) to output mode */
+ reg = readw(IO_CNTL_REG);
+ reg &= ~(1 << 3);
+ writew(reg, IO_CNTL_REG);
+
+ /* LCD Set I/O(3) output low */
+ reg = readw(ARMIO_LATCH_OUT);
+ reg &= ~(1 << 3);
+ writew(reg, ARMIO_LATCH_OUT);
+}
+
+void board_init(void)
+{
+ /* Configure the memory interface */
+ calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS2, 5, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS3, 5, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_CS4, 0, CALYPSO_MEM_8bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS6, 0, CALYPSO_MEM_32bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS7, 0, CALYPSO_MEM_32bit, 0);
+
+ /* Set VTCXO_DIV2 = 1, configure PLL for 104 MHz and give ARM half of that */
+ calypso_clock_set(2, CALYPSO_PLL13_104_MHZ, ARM_MCLK_DIV_2);
+
+ /* Configure the RHEA bridge with some sane default values */
+ calypso_rhea_cfg(0, 0, 0xff, 0, 1, 0, 0);
+
+ /* Initialize board-specific GPIO */
+ board_io_init();
+
+ /* Enable bootrom mapping to route exception vectors to RAM */
+ calypso_bootrom(1);
+ calypso_exceptions_install();
+
+ /* Initialize interrupt controller */
+ irq_init();
+
+ /* initialize MODEM UART to be used for sercomm*/
+ uart_init(SERCOMM_UART_NR, 1);
+ uart_baudrate(SERCOMM_UART_NR, UART_115200);
+
+ /* Initialize IRDA UART to be used for old-school console code.
+ * note: IRDA uart only accessible on C115 and C117 PCB */
+ uart_init(CONS_UART_NR, 1);
+ uart_baudrate(CONS_UART_NR, UART_115200);
+
+ /* Initialize hardware timers */
+ hwtimer_init();
+
+ /* Initialize DMA controller */
+ dma_init();
+
+ /* Initialize real time clock */
+ rtc_init();
+
+ /* Initialize system timers (uses hwtimer 2) */
+ timer_init();
+
+ /* Initialize LCD driver (uses I2C) and backlight */
+ display = &st7558_display;
+ display_init();
+ bl_mode_pwl(1);
+ bl_level(50);
+
+ /* Initialize keypad driver */
+ keypad_init(1);
+
+ /* Initialize ABB driver (uses SPI) */
+ twl3025_init();
+}
diff --git a/Src/osmocombb/src/target/firmware/board/compal_e88/loader.lds b/Src/osmocombb/src/target/firmware/board/compal_e88/loader.lds
new file mode 100644
index 0000000..a7a001f
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal_e88/loader.lds
@@ -0,0 +1,147 @@
+/*
+ * Linker script for flashed loader on the Compal E88
+ *
+ * This script creates a binary that can replace a standard firmware
+ * located at 0x2000. It works in conjunction with the compal ramloader.
+ *
+ * The interrupt vectors and start address are at known, fixed offsets.
+ *
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+MEMORY
+{
+ /* 2 MBytes of external flash memory */
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x200000
+ /* 256 kBytes of internal zero-waitstate sram */
+ IRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x040000
+ /* 256 kBytes of external slow sram */
+ ERAM (rw) : ORIGIN = 0x01000000, LENGTH = 0x040000
+}
+SECTIONS
+{
+ /* Provide symbols for the compal loader */
+ .compal.loader 0x00000000 (NOLOAD) : {
+ _compal_loader_start = .;
+ . = 0x2000;
+ _compal_loader_end = .;
+ } > FLASH
+
+ /* Compal-style image header */
+ .compal.header 0x00002000 : {
+ _compal_header_start = .;
+ KEEP(*(.compal.header))
+ *(.compal.header)
+ . = 0xA0;
+ _compal_header_end = .;
+ } > FLASH
+
+ /* Compal-style vector table */
+ .compal.vectors 0x000020A0 : {
+ PROVIDE(_exceptions = .);
+ KEEP(*(.text.exceptions))
+ *(.text.exceptions)
+ } > FLASH
+
+ /* Compal-style entry point */
+ .text.start 0x000020F8 : {
+ PROVIDE(_start = .);
+ KEEP(*(.text.start))
+ *(.text.start)
+ } > FLASH
+
+ /* code */
+ .text : {
+ /* regular code */
+ *(.text*)
+ /* gcc voodoo */
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)
+ } > FLASH
+ PROVIDE(_text_start = ADDR(.text));
+ PROVIDE(_text_end = ADDR(.text) + SIZEOF(.text));
+
+ /* constructor pointers */
+ .ctors : {
+ /* ctor count */
+ LONG(SIZEOF(.ctors) / 4 - 2)
+ /* ctor pointers */
+ KEEP(*(SORT(.ctors)))
+ /* end of list */
+ LONG(0)
+ } > FLASH
+ PROVIDE(_ctor_start = LOADADDR(.ctors));
+ PROVIDE(_ctor_end = LOADADDR(.ctors) + SIZEOF(.ctors));
+
+ /* destructor pointers */
+ .dtors : {
+ /* dtor count */
+ LONG(SIZEOF(.dtors) / 4 - 2)
+ /* dtor pointers */
+ KEEP(*(SORT(.dtors)))
+ /* end of list */
+ LONG(0)
+ } > FLASH
+ PROVIDE(_dtor_start = LOADADDR(.dtors));
+ PROVIDE(_dtor_end = LOADADDR(.dtors) + SIZEOF(.dtors));
+
+ /* read-only data */
+ .rodata : {
+ *(.rodata*)
+ } > FLASH
+ PROVIDE(_rodata_start = ADDR(.rodata));
+ PROVIDE(_rodata_end = ADDR(.rodata) + SIZEOF(.rodata));
+
+ /* pic offset tables */
+ .got : {
+ . = ALIGN(4);
+ *(.got)
+ *(.got.plt) *(.igot.plt) *(.got) *(.igot)
+ . = ALIGN(4);
+ } > FLASH
+ PROVIDE(_got_start = ADDR(.got));
+ PROVIDE(_got_end = ADDR(.got) + SIZEOF(.got));
+
+ /* reserved ram */
+ .compal.reservedram 0x800000 (NOLOAD) : {
+ . = 0xff;
+ } > IRAM
+
+ /* initialized data */
+ .data : AT (LOADADDR(.got) + SIZEOF(.got)) {
+ . = ALIGN(4);
+ *(.data)
+ . = ALIGN(4);
+ } > IRAM
+ PROVIDE(__data_start = LOADADDR(.data));
+ PROVIDE(__data_end = LOADADDR(.data) + SIZEOF(.data));
+ PROVIDE(_data_start = ADDR(.data));
+ PROVIDE(_data_end = ADDR(.data) + SIZEOF(.data));
+
+ /* ram code */
+ .ramtext : AT (LOADADDR(.data) + SIZEOF(.data)) {
+ . = ALIGN(4);
+ *(.ramtext)
+ . = ALIGN(4);
+ } > IRAM
+ PROVIDE(__ramtext_start = LOADADDR(.ramtext));
+ PROVIDE(__ramtext_end = LOADADDR(.ramtext) + SIZEOF(.ramtext));
+ PROVIDE(_ramtext_start = ADDR(.ramtext));
+ PROVIDE(_ramtext_end = ADDR(.ramtext) + SIZEOF(.ramtext));
+
+ /* uninitialized data */
+ .bss (NOLOAD) : {
+ . = ALIGN(4);
+ *(.bss)
+ . = ALIGN(4);
+ } > IRAM
+ PROVIDE(__bss_start = ADDR(.bss));
+ PROVIDE(__bss_end = ADDR(.bss) + SIZEOF(.bss));
+ PROVIDE(_bss_start = __bss_start);
+ PROVIDE(_bss_end = __bss_end);
+
+ /* end of image */
+ . = ALIGN(4);
+ _end = .;
+ PROVIDE(end = .);
+}
diff --git a/Src/osmocombb/src/target/firmware/board/compal_e99/init.c b/Src/osmocombb/src/target/firmware/board/compal_e99/init.c
new file mode 100644
index 0000000..0c218a8
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/compal_e99/init.c
@@ -0,0 +1,140 @@
+/* Initialization for the Compal E99 (Motorola C155) */
+
+/* (C) 2010 by Harald Welte <laforge@gnumonks.org>
+ * (C) 2010 by Steve Markgraf <steve@steve-m.de>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include <debug.h>
+#include <ctors.h>
+#include <memory.h>
+#include <board.h>
+#include <keypad.h>
+#include <console.h>
+#include <flash/cfi_flash.h>
+
+#include <calypso/irq.h>
+#include <calypso/clock.h>
+#include <calypso/dma.h>
+#include <calypso/rtc.h>
+#include <calypso/timer.h>
+#include <uart.h>
+#include <calypso/backlight.h>
+
+#include <comm/sercomm.h>
+
+#include <abb/twl3025.h>
+#include <rf/trf6151.h>
+#include <display.h>
+
+#define ARMIO_LATCH_OUT 0xfffe4802
+#define IO_CNTL_REG 0xfffe4804
+#define ASIC_CONF_REG 0xfffef008
+
+static void board_io_init(void)
+{
+ uint16_t reg;
+
+ reg = readw(ASIC_CONF_REG);
+ /* LCD Set I/O(3) / SA0 to I/O(3) mode */
+ reg &= ~( (1 << 12) | (1 << 10) | (1 << 7) | (1 << 1)) ;
+ /* don't set function pins to I2C Mode, C155 uses UWire */
+ /* TWL3025: Set SPI+RIF RX clock to rising edge */
+ reg |= (1 << 13) | (1 << 14);
+ writew(reg, ASIC_CONF_REG);
+
+ /* LCD Set I/O(3) to output mode and enable C155 backlight (IO1) */
+ /* FIXME: Put the display backlight control to backlight.c */
+ reg = readw(IO_CNTL_REG);
+ reg &= ~( (1 << 3) | (1 << 1));
+ writew(reg, IO_CNTL_REG);
+
+ /* LCD Set I/O(3) output low */
+ reg = readw(ARMIO_LATCH_OUT);
+ reg &= ~(1 << 3);
+ reg |= (1 << 1);
+ writew(reg, ARMIO_LATCH_OUT);
+}
+
+void board_init(void)
+{
+ /* Disable watchdog (compal loader leaves it enabled) */
+ wdog_enable(0);
+
+ /* Configure memory interface */
+ calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS2, 5, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS3, 5, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_CS4, 0, CALYPSO_MEM_8bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS6, 0, CALYPSO_MEM_32bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS7, 0, CALYPSO_MEM_32bit, 0);
+
+ /* Set VTCXO_DIV2 = 1, configure PLL for 104 MHz and give ARM half of that */
+ calypso_clock_set(2, CALYPSO_PLL13_104_MHZ, ARM_MCLK_DIV_2);
+
+ /* Configure the RHEA bridge with some sane default values */
+ calypso_rhea_cfg(0, 0, 0xff, 0, 1, 0, 0);
+
+ /* Initialize board-specific GPIO */
+ board_io_init();
+
+ /* Enable bootrom mapping to route exception vectors to RAM */
+ calypso_bootrom(1);
+ calypso_exceptions_install();
+
+ /* Initialize interrupt controller */
+ irq_init();
+
+ /* initialize MODEM UART to be used for sercomm*/
+ uart_init(SERCOMM_UART_NR, 1);
+ uart_baudrate(SERCOMM_UART_NR, UART_115200);
+
+ /* initialize IRDA UART to be used for old-school console code.
+ * note: IRDA uart only accessible on C115 and C117 PCB */
+ uart_init(CONS_UART_NR, 1);
+ uart_baudrate(CONS_UART_NR, UART_115200);
+
+ /* Initialize hardware timers */
+ hwtimer_init();
+
+ /* Initialize DMA controller */
+ dma_init();
+
+ /* Initialize real time clock */
+ rtc_init();
+
+ /* Initialize system timers (uses hwtimer 2) */
+ timer_init();
+
+ /* Initialize LCD driver (uses UWire) and backlight */
+ display = &ssd1783_display;
+ display_init();
+ bl_mode_pwl(1);
+ bl_level(50);
+
+ /* Initialize keypad driver */
+ keypad_init(1);
+
+ /* Initialize ABB driver (uses SPI) */
+ twl3025_init();
+}
diff --git a/Src/osmocombb/src/target/firmware/board/gta0x/init.c b/Src/osmocombb/src/target/firmware/board/gta0x/init.c
new file mode 100644
index 0000000..4f256ea
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/gta0x/init.c
@@ -0,0 +1,136 @@
+/* Initialization for the Openmoko Freerunner modem */
+
+/* (C) 2010 by Harald Welte <laforge@gnumonks.org>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include <debug.h>
+#include <ctors.h>
+#include <memory.h>
+#include <board.h>
+#include <keypad.h>
+#include <console.h>
+#include <flash/cfi_flash.h>
+
+#include <calypso/irq.h>
+#include <calypso/clock.h>
+#include <calypso/dma.h>
+#include <calypso/rtc.h>
+#include <calypso/timer.h>
+#include <uart.h>
+#include <calypso/backlight.h>
+
+#include <comm/sercomm.h>
+#include <comm/timer.h>
+
+#include <abb/twl3025.h>
+#include <rf/trf6151.h>
+#include <display.h>
+
+#define ARMIO_LATCH_OUT 0xfffe4802
+#define IO_CNTL_REG 0xfffe4804
+#define ASIC_CONF_REG 0xfffef008
+
+static void board_io_init(void)
+{
+ uint16_t reg;
+
+ reg = readw(ASIC_CONF_REG);
+ /* LCD Set I/O(3) / SA0 to I/O(3) mode */
+ reg &= ~(1 << 10);
+ /* Set function pins to I2C Mode */
+ reg |= ((1 << 12) | (1 << 7)); /* SCL / SDA */
+ /* TWL3025: Set SPI+RIF RX clock to rising edge */
+ reg |= (1 << 13) | (1 << 14);
+ writew(reg, ASIC_CONF_REG);
+
+ /* LCD Set I/O(3) to output mode */
+ reg = readw(IO_CNTL_REG);
+ reg &= ~(1 << 3);
+ writew(reg, IO_CNTL_REG);
+
+ /* LCD Set I/O(3) output low */
+ reg = readw(ARMIO_LATCH_OUT);
+ reg &= ~(1 << 3);
+ writew(reg, ARMIO_LATCH_OUT);
+}
+
+void board_init(void)
+{
+ /* Configure the memory interface */
+ calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS2, 5, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS3, 5, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_CS4, 0, CALYPSO_MEM_8bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS6, 0, CALYPSO_MEM_32bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS7, 0, CALYPSO_MEM_32bit, 0);
+
+ /* Set VTCXO_DIV2 = 1, configure PLL for 104 MHz and give ARM half of that */
+ calypso_clock_set(2, CALYPSO_PLL13_104_MHZ, ARM_MCLK_DIV_2);
+
+ /* Configure the RHEA bridge with some sane default values */
+ calypso_rhea_cfg(0, 0, 0xff, 0, 1, 0, 0);
+
+ /* Initialize board-specific GPIO */
+ board_io_init();
+
+ /* Enable bootrom mapping to route exception vectors to RAM */
+ calypso_bootrom(1);
+ calypso_exceptions_install();
+
+ /* Initialize interrupt controller */
+ irq_init();
+
+ /* initialize MODEM UART to be used for sercomm*/
+ uart_init(SERCOMM_UART_NR, 1);
+ uart_baudrate(SERCOMM_UART_NR, UART_115200);
+
+ /* Initialize IRDA UART to be used for old-school console code.
+ * note: IRDA uart only accessible on C115 and C117 PCB */
+ uart_init(CONS_UART_NR, 1);
+ uart_baudrate(CONS_UART_NR, UART_115200);
+
+ /* Initialize hardware timers */
+ hwtimer_init();
+
+ /* Initialize DMA controller */
+ dma_init();
+
+ /* Initialize real time clock */
+ rtc_init();
+
+ /* Initialize system timers (uses hwtimer 2) */
+ timer_init();
+
+ /* Initialize LCD driver (uses I2C) and backlight */
+ display = &st7558_display;
+ display_init();
+ bl_mode_pwl(1);
+ bl_level(50);
+
+ /* Initialize keypad driver */
+ keypad_init(1);
+
+ /* Initialize ABB driver (uses SPI) */
+ twl3025_init();
+}
diff --git a/Src/osmocombb/src/target/firmware/board/gta0x/rf_power.c b/Src/osmocombb/src/target/firmware/board/gta0x/rf_power.c
new file mode 100644
index 0000000..1c896f7
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/gta0x/rf_power.c
@@ -0,0 +1,63 @@
+/* Tx RF power calibration for the FIC GTA0x phones */
+
+/* (C) 2010 by Harald Welte <laforge@gnumonks.org>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <stdint.h>
+#include <osmocom/core/utils.h>
+
+/* GSM900 ARFCN 33, Measurements by Steve Markgraf / May 2010 */
+/* FIXME those are from compal ... need real GTA calibration */
+const int16_t dbm2apc_gsm900[] = {
+ [0] = 151,
+ [1] = 152,
+ [2] = 153,
+ [3] = 155,
+ [4] = 156,
+ [5] = 158,
+ [6] = 160,
+ [7] = 162,
+ [8] = 164,
+ [9] = 167,
+ [10] = 170,
+ [11] = 173,
+ [12] = 177,
+ [13] = 182,
+ [14] = 187,
+ [15] = 192,
+ [16] = 199,
+ [17] = 206,
+ [18] = 214,
+ [19] = 223,
+ [20] = 233,
+ [21] = 244,
+ [22] = 260,
+ [23] = 271,
+ [24] = 288,
+ [25] = 307,
+ [26] = 327,
+ [27] = 350,
+ [28] = 376,
+ [29] = 407,
+ [30] = 456,
+ [31] = 575,
+};
+
+const int dbm2apc_gsm900_max = ARRAY_SIZE(dbm2apc_gsm900) - 1;
diff --git a/Src/osmocombb/src/target/firmware/board/gta0x/rffe_gta0x_triband.c b/Src/osmocombb/src/target/firmware/board/gta0x/rffe_gta0x_triband.c
new file mode 100644
index 0000000..f118d29
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/gta0x/rffe_gta0x_triband.c
@@ -0,0 +1,131 @@
+#include <stdint.h>
+#include <stdio.h>
+
+#include <debug.h>
+#include <memory.h>
+#include <rffe.h>
+#include <calypso/tsp.h>
+#include <rf/trf6151.h>
+
+/* This is a value that has been measured on the C123 by Harald: 71dBm,
+ it is the difference between the input level at the antenna and what
+ the DSP reports, subtracted by the total gain of the TRF6151 */
+#define SYSTEM_INHERENT_GAIN 71
+
+/* describe how the RF frontend is wired on the Openmoko GTA0x boards */
+
+#define RITA_RESET TSPACT(0) /* Reset of the Rita TRF6151 */
+#define PA_ENABLE TSPACT(9) /* Enable the Power Amplifier */
+#define GSM_TXEN TSPACT(3) /* PA GSM switch, low-active */
+
+/* All VCn controls are low-active */
+#define ASM_VC1 TSPACT(2) /* Antenna switch VC1 */
+#define ASM_VC2 TSPACT(1) /* Antenna switch VC2 */
+#define ASM_VC3 TSPACT(4) /* Antenna switch VC3 */
+
+#define IOTA_STROBE TSPEN(0) /* Strobe for the Iota TSP */
+#define RITA_STROBE TSPEN(2) /* Strobe for the Rita TSP */
+
+/* switch RF Frontend Mode */
+void rffe_mode(enum gsm_band band, int tx)
+{
+ uint16_t tspact = tsp_act_state();
+
+ /* First we mask off all bits from the state cache */
+ tspact &= ~PA_ENABLE;
+ tspact &= ~GSM_TXEN;
+ tspact |= ASM_VC1 | ASM_VC2 | ASM_VC3; /* low-active */
+
+ switch (band) {
+ case GSM_BAND_850:
+ case GSM_BAND_900:
+ case GSM_BAND_1800:
+ break;
+ case GSM_BAND_1900:
+ tspact &= ~ASM_VC2;
+ break;
+ default:
+ /* TODO return/signal error here */
+ break;
+ }
+
+#ifdef CONFIG_TX_ENABLE
+ /* Then we selectively set the bits on, if required */
+ if (tx) {
+ switch (band) {
+ case GSM_BAND_850:
+ case GSM_BAND_900:
+ tspact &= ~ASM_VC3;
+ break;
+ case GSM_BAND_1800:
+ case GSM_BAND_1900:
+ tspact &= ~ASM_VC1;
+ tspact |= ASM_VC2;
+ tspact |= GSM_TXEN;
+ break;
+ default:
+ break;
+ }
+ tspact |= PA_ENABLE;
+ }
+#endif /* TRANSMIT_SUPPORT */
+
+ tsp_act_update(tspact);
+}
+
+/* Returns RF wiring */
+uint32_t rffe_get_rx_ports(void)
+{
+ return (1 << PORT_LO) | (1 << PORT_DCS1800) | (1 << PORT_PCS1900);
+}
+
+uint32_t rffe_get_tx_ports(void)
+{
+ return (1 << PORT_LO) | (1 << PORT_HI);
+}
+
+
+#define MCU_SW_TRACE 0xfffef00e
+#define ARM_CONF_REG 0xfffef006
+
+void rffe_init(void)
+{
+ uint16_t reg;
+
+ reg = readw(ARM_CONF_REG);
+ reg &= ~ (1 << 7); /* TSPACT4 I/O function, not nRDYMEM */
+ writew(reg, ARM_CONF_REG);
+
+ reg = readw(MCU_SW_TRACE);
+ reg &= ~(1 << 1); /* TSPACT9 I/O function, not MAS(1) */
+ writew(reg, MCU_SW_TRACE);
+
+ /* Configure the TSPEN which is connected to the TWL3025 */
+ tsp_setup(IOTA_STROBE, 1, 0, 0);
+
+ trf6151_init(RITA_STROBE, RITA_RESET);
+}
+
+uint8_t rffe_get_gain(void)
+{
+ return trf6151_get_gain();
+}
+
+void rffe_set_gain(uint8_t dbm)
+{
+ trf6151_set_gain(dbm);
+}
+
+const uint8_t system_inherent_gain = SYSTEM_INHERENT_GAIN;
+
+/* Given the expected input level of exp_inp dBm/8 and the target of target_bb
+ * dBm8, configure the RF Frontend with the respective gain */
+void rffe_compute_gain(int16_t exp_inp, int16_t target_bb)
+{
+ trf6151_compute_gain(exp_inp, target_bb);
+}
+
+void rffe_rx_win_ctrl(int16_t exp_inp, int16_t target_bb)
+{
+ /* FIXME */
+}
diff --git a/Src/osmocombb/src/target/firmware/board/manifest.c b/Src/osmocombb/src/target/firmware/board/manifest.c
new file mode 100644
index 0000000..025a722
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/manifest.c
@@ -0,0 +1,7 @@
+
+#include "manifest.h"
+
+const char *manifest_application = APPLICATION;
+const char *manifest_revision = GIT_REVISION;
+const char *manifest_board = BOARD;
+const char *manifest_environment = ENVIRONMENT;
diff --git a/Src/osmocombb/src/target/firmware/board/mediatek/macros.S b/Src/osmocombb/src/target/firmware/board/mediatek/macros.S
new file mode 100644
index 0000000..14ee6e6
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/mediatek/macros.S
@@ -0,0 +1,76 @@
+
+.macro clear_bss
+ mov r0, #0
+ ldr r1, =__bss_start
+ ldr r2, =__bss_end
+loop_bss:
+ cmp r1, r2
+ strlo r0, [r1], #4
+ blo loop_bss
+.endm
+
+.macro copy_data
+ ldr r0, =__data_start
+ ldr r1, =_data_start
+ ldr r2, =__data_end
+ cmp r0, r2
+ beq done_data
+loop_data:
+ ldrb r4, [r0], #1
+ strb r4, [r1], #1
+ cmp r0, r2
+ bne loop_data
+done_data:
+.endm
+
+.macro copy_ramtext
+ ldr r0, =__ramtext_start
+ ldr r1, =_ramtext_start
+ ldr r2, =__ramtext_end
+ cmp r0, r2
+ beq done_ramtext
+loop_ramtext:
+ ldrb r4, [r0], #1
+ strb r4, [r1], #1
+ cmp r0, r2
+ bne loop_ramtext
+done_ramtext:
+.endm
+
+ .EQU ARM_MODE_FIQ, 0x11
+ .EQU ARM_MODE_IRQ, 0x12
+ .EQU ARM_MODE_SVC, 0x13
+
+ .EQU I_BIT, 0x80
+ .EQU F_BIT, 0x40
+
+#define TOP_OF_RAM 0x4000a000
+#define FIQ_STACK_SIZE 1024
+#define IRQ_STACK_SIZE 1024
+
+.macro init_stacks
+ /* initialize stacks, starting at TOP_OF_RAM */
+ ldr r0, =TOP_OF_RAM
+
+ /* initialize FIQ stack */
+ msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
+ mov r13, r0
+ sub r0, r0, #FIQ_STACK_SIZE
+
+ /* initialize IRQ stack */
+ msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
+ mov r13, r0
+ sub r0, r0, #IRQ_STACK_SIZE
+
+ /* initialize supervisor stack */
+ msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT
+ mov r13, r0
+.endm
+
+.macro call_ctors
+ /* call constructor functions */
+ ldr r0, =_ctor_start
+ ldr r1, =_ctor_end
+ bl do_global_ctors
+.endm
+
diff --git a/Src/osmocombb/src/target/firmware/board/mediatek/ram.lds b/Src/osmocombb/src/target/firmware/board/mediatek/ram.lds
new file mode 100644
index 0000000..a2af560
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/mediatek/ram.lds
@@ -0,0 +1,112 @@
+/*
+ * Linker script for running from internal SRAM on MTK phones
+ *
+ * This script is tailored specifically to the requirements imposed
+ * on us by the Mediatek bootloader.
+ *
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+MEMORY
+{
+ /* mtk-loaded binary: our text, initialized data */
+ LRAM (rw) : ORIGIN = 0x40000000, LENGTH = 0x00006000
+ /* mtk-loaded binary: our unitialized data, stacks, heap */
+ IRAM (rw) : ORIGIN = 0x40006000, LENGTH = 0x00006000
+}
+SECTIONS
+{
+ . = 0x40000000;
+
+ /* romloader data section, contains passthru interrupt vectors */
+ .mtk.loader (NOLOAD) : { . = 0x1400; } > LRAM
+
+ /* initialization code */
+ . = ALIGN(4);
+ .text.start : {
+ PROVIDE(_start = .);
+ KEEP(*(.text.start))
+ *(.text.start)
+ } > LRAM
+
+ /* code */
+ . = ALIGN(4);
+ .text (LOADADDR(.text.start) + SIZEOF(.text.start)) :
+ AT (LOADADDR(.text.start) + SIZEOF(.text.start)) {
+ /* regular code */
+ *(.text*)
+ /* always-in-ram code */
+ *(.ramtext*)
+ /* gcc voodoo */
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)
+ . = ALIGN(4);
+ } > LRAM
+ PROVIDE(_text_start = LOADADDR(.text));
+ PROVIDE(_text_end = LOADADDR(.text) + SIZEOF(.text));
+
+ /* constructor pointers */
+ .ctors : {
+ /* ctor count */
+ LONG(SIZEOF(.ctors) / 4 - 2)
+ /* ctor pointers */
+ KEEP(*(SORT(.ctors)))
+ /* end of list */
+ LONG(0)
+ } > LRAM
+ PROVIDE(_ctor_start = LOADADDR(.ctors));
+ PROVIDE(_ctor_end = LOADADDR(.ctors) + SIZEOF(.ctors));
+
+ /* destructor pointers */
+ .dtors : {
+ /* dtor count */
+ LONG(SIZEOF(.dtors) / 4 - 2)
+ /* dtor pointers */
+ KEEP(*(SORT(.dtors)))
+ /* end of list */
+ LONG(0)
+ } > LRAM
+ PROVIDE(_dtor_start = LOADADDR(.dtors));
+ PROVIDE(_dtor_end = LOADADDR(.dtors) + SIZEOF(.dtors));
+
+ /* read-only data */
+ . = ALIGN(4);
+ .rodata : {
+ *(.rodata*)
+ } > LRAM
+ PROVIDE(_rodata_start = LOADADDR(.rodata));
+ PROVIDE(_rodata_end = LOADADDR(.rodata) + SIZEOF(.rodata));
+
+ /* initialized data */
+ . = ALIGN(4);
+ .data : {
+ *(.data)
+ } > LRAM
+ PROVIDE(_data_start = LOADADDR(.data));
+ PROVIDE(_data_end = LOADADDR(.data) + SIZEOF(.data));
+
+ /* pic offset tables */
+ . = ALIGN(4);
+ .got : {
+ *(.got)
+ *(.got.plt) *(.igot.plt) *(.got) *(.igot)
+ } > LRAM
+ PROVIDE(_got_start = LOADADDR(.got));
+ PROVIDE(_got_end = LOADADDR(.got) + SIZEOF(.got));
+
+ /* uninitialized data */
+ .bss (NOLOAD) : {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss)
+ } > IRAM
+ . = ALIGN(4);
+ __bss_end = .;
+ PROVIDE(_bss_start = __bss_start);
+ PROVIDE(_bss_end = __bss_end);
+
+ /* end of image */
+ . = ALIGN(4);
+ _end = .;
+ PROVIDE(end = .);
+}
diff --git a/Src/osmocombb/src/target/firmware/board/mediatek/start.ram.S b/Src/osmocombb/src/target/firmware/board/mediatek/start.ram.S
new file mode 100644
index 0000000..c8f242c
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/mediatek/start.ram.S
@@ -0,0 +1,26 @@
+
+.section .text.start
+
+#include "macros.S"
+
+.globl _start
+_start:
+ /* clear bss section */
+ clear_bss
+
+ /* initialize all stacks */
+ init_stacks
+
+ /* call constructors */
+ call_ctors
+
+ /* jump to main */
+ ldr pc, _jump_main
+
+ /* endless loop at end of program */
+_loop:
+ b _loop
+ b _start
+
+_jump_main:
+ .word main
diff --git a/Src/osmocombb/src/target/firmware/board/mediatek/uart.c b/Src/osmocombb/src/target/firmware/board/mediatek/uart.c
new file mode 100644
index 0000000..8e86b20
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/mediatek/uart.c
@@ -0,0 +1,424 @@
+/* MediaTek MT62xx internal UART Driver
+ *
+ * based on the Calypso driver, so there might be some cruft from it left...
+ *
+ * (C) 2010 by Harald Welte <laforge@gnumonks.org>
+ * (C) 2010 by Ingo Albrecht <prom@berlin.ccc.de>
+ * (C) 2010 by Steve Markgraf <steve@steve-m.de>
+ * (C) 2011 by Wolfram Sang <wolfram@the-dreams.de>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <debug.h>
+#include <memory.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdio.h>
+#include <defines.h>
+#include <uart.h>
+#include <console.h>
+
+#include <comm/sercomm.h>
+
+/* MT622x */
+#if 0
+#define BASE_ADDR_UART1 0x80130000
+#define BASE_ADDR_UART2 0x80180000
+#define BASE_ADDR_UART3 0x801b0000
+#endif
+
+/* MT 6235 */
+#define BASE_ADDR_UART1 0x81030000
+
+//TODO make UART2 and 3 work
+#define UART_REG(n,m) (BASE_ADDR_UART1 + (m))
+
+#define LCR7BIT 0x80
+#define LCRBFBIT 0x40
+#define MCR6BIT 0x20
+#define REG_OFFS(m) ((m) & ~(LCR7BIT|LCRBFBIT|MCR6BIT))
+/* read access LCR[7] = 0 */
+enum uart_reg {
+ RBR = 0x00,
+ IER = 0x04,
+ IIR = 0x08,
+ LCR = 0x0c,
+ MCR = 0x10,
+ LSR = 0x14,
+ MSR = 0x18,
+ SCR = 0x1c,
+ AUTOBAUD_EN = 0x20,
+ HIGHSPEED = 0x24,
+ SAMPLE_COUNT = 0x28,
+ SAMPLE_POINT = 0x2c,
+ AUTOBAUD_REG = 0x30,
+ RATE_FIX_REG = 0x34, /* undocumented */
+ AUTOBAUDSAMPLE = 0x38,
+ GUARD = 0x3c,
+ ESCAPE_DAT = 0x40,
+ ESCAPE_EN = 0x44,
+ SLEEP_EN = 0x48,
+ VFIFO_EN = 0x4c,
+/* read access LCR[7] = 1 */
+ DLL = RBR,
+ DLH = IER,
+/* read/write access LCR[7:0] = 0xbf */
+ EFR = IIR | LCRBFBIT,
+ XON1 = MCR | LCRBFBIT,
+ XON2 = LSR | LCRBFBIT,
+ XOFF1 = MSR | LCRBFBIT,
+ XOFF2 = SCR | LCRBFBIT,
+};
+
+enum fcr_bits {
+ FIFO_EN = (1 << 0),
+ RX_FIFO_CLEAR = (1 << 1),
+ TX_FIFO_CLEAR = (1 << 2),
+ DMA_MODE = (1 << 3),
+};
+#define TX_FIFO_TRIG_SHIFT 4
+#define RX_FIFO_TRIG_SHIFT 6
+
+enum iir_bits {
+ IIR_INT_PENDING = 0x01,
+ IIR_INT_TYPE = 0x3E,
+ IIR_INT_TYPE_RX_STATUS_ERROR = 0x06,
+ IIR_INT_TYPE_RX_TIMEOUT = 0x0C,
+ IIR_INT_TYPE_RBR = 0x04,
+ IIR_INT_TYPE_THR = 0x02,
+ IIR_INT_TYPE_MSR = 0x00,
+ IIR_INT_TYPE_XOFF = 0x10,
+ IIR_INT_TYPE_FLOW = 0x20,
+ IIR_FCR0_MIRROR = 0xC0,
+};
+
+
+/* enable or disable the divisor latch for access to DLL, DLH */
+static void uart_set_lcr7bit(int uart, int on)
+{
+ uint8_t reg;
+
+ reg = readb(UART_REG(uart, LCR));
+ if (on)
+ reg |= (1 << 7);
+ else
+ reg &= ~(1 << 7);
+ writeb(reg, UART_REG(uart, LCR));
+}
+
+static uint8_t old_lcr;
+static void uart_set_lcr_bf(int uart, int on)
+{
+ if (on) {
+ old_lcr = readb(UART_REG(uart, LCR));
+ writeb(0xBF, UART_REG(uart, LCR));
+ } else {
+ writeb(old_lcr, UART_REG(uart, LCR));
+ }
+}
+
+/* Enable or disable the TCR_TLR latch bit in MCR[6] */
+static void uart_set_mcr6bit(int uart, int on)
+{
+ uint8_t mcr;
+ /* we assume EFR[4] is always set to 1 */
+ mcr = readb(UART_REG(uart, MCR));
+ if (on)
+ mcr |= (1 << 6);
+ else
+ mcr &= ~(1 << 6);
+ writeb(mcr, UART_REG(uart, MCR));
+}
+
+static void uart_reg_write(int uart, enum uart_reg reg, uint8_t val)
+{
+ if (reg & LCRBFBIT)
+ uart_set_lcr_bf(uart, 1);
+ else if (reg & LCR7BIT)
+ uart_set_lcr7bit(uart, 1);
+ else if (reg & MCR6BIT)
+ uart_set_mcr6bit(uart, 1);
+
+ writeb(val, UART_REG(uart, REG_OFFS(reg)));
+
+ if (reg & LCRBFBIT)
+ uart_set_lcr_bf(uart, 0);
+ else if (reg & LCR7BIT)
+ uart_set_lcr7bit(uart, 0);
+ else if (reg & MCR6BIT)
+ uart_set_mcr6bit(uart, 0);
+}
+
+/* read from a UART register, applying any required latch bits */
+static uint8_t uart_reg_read(int uart, enum uart_reg reg)
+{
+ uint8_t ret;
+
+ if (reg & LCRBFBIT)
+ uart_set_lcr_bf(uart, 1);
+ else if (reg & LCR7BIT)
+ uart_set_lcr7bit(uart, 1);
+ else if (reg & MCR6BIT)
+ uart_set_mcr6bit(uart, 1);
+
+ ret = readb(UART_REG(uart, REG_OFFS(reg)));
+
+ if (reg & LCRBFBIT)
+ uart_set_lcr_bf(uart, 0);
+ else if (reg & LCR7BIT)
+ uart_set_lcr7bit(uart, 0);
+ else if (reg & MCR6BIT)
+ uart_set_mcr6bit(uart, 0);
+
+ return ret;
+}
+
+static void uart_irq_handler_cons(__unused int irqnr)
+{
+ const uint8_t uart = CONS_UART_NR;
+ uint8_t iir;
+
+ //uart_putchar_nb(uart, 'U');
+
+ iir = uart_reg_read(uart, IIR);
+ if (iir & IIR_INT_PENDING)
+ return;
+
+ switch (iir & IIR_INT_TYPE) {
+ case IIR_INT_TYPE_RBR:
+ break;
+ case IIR_INT_TYPE_THR:
+ if (cons_rb_flush() == 1) {
+ /* everything was flushed, disable RBR IRQ */
+ uint8_t ier = uart_reg_read(uart, IER);
+ ier &= ~(1 << 1);
+ uart_reg_write(uart, IER, ier);
+ }
+ break;
+ case IIR_INT_TYPE_MSR:
+ break;
+ case IIR_INT_TYPE_RX_STATUS_ERROR:
+ break;
+ case IIR_INT_TYPE_RX_TIMEOUT:
+ break;
+ case IIR_INT_TYPE_XOFF:
+ break;
+ }
+}
+
+static void uart_irq_handler_sercomm(__unused int irqnr)
+{
+ const uint8_t uart = SERCOMM_UART_NR;
+ uint8_t iir, ch;
+
+ //uart_putchar_nb(uart, 'U');
+
+ iir = uart_reg_read(uart, IIR);
+ if (iir & IIR_INT_PENDING)
+ return;
+
+ switch (iir & IIR_INT_TYPE) {
+ case IIR_INT_TYPE_RX_TIMEOUT:
+ case IIR_INT_TYPE_RBR:
+ /* as long as we have rx data available */
+ while (uart_getchar_nb(uart, &ch)) {
+ if (sercomm_drv_rx_char(ch) < 0) {
+ /* sercomm cannot receive more data right now */
+ uart_irq_enable(uart, UART_IRQ_RX_CHAR, 0);
+ }
+ }
+ break;
+ case IIR_INT_TYPE_THR:
+ /* as long as we have space in the FIFO */
+ while (!uart_tx_busy(uart)) {
+ /* get a byte from sercomm */
+ if (!sercomm_drv_pull(&ch)) {
+ /* no more bytes in sercomm, stop TX interrupts */
+ uart_irq_enable(uart, UART_IRQ_TX_EMPTY, 0);
+ break;
+ }
+ /* write the byte into the TX FIFO */
+ uart_putchar_nb(uart, ch);
+ }
+ break;
+ case IIR_INT_TYPE_MSR:
+ printf("UART IRQ MSR\n");
+ break;
+ case IIR_INT_TYPE_RX_STATUS_ERROR:
+ printf("UART IRQ RX_SE\n");
+ break;
+ case IIR_INT_TYPE_XOFF:
+ printf("UART IRQXOFF\n");
+ break;
+ }
+}
+
+void uart_init(uint8_t uart, __unused uint8_t interrupts)
+{
+ /* no interrupts, only polling so far */
+
+ uart_reg_write(uart, IER, 0x00);
+ if (uart == CONS_UART_NR) {
+ cons_init();
+ } else {
+ sercomm_init();
+ uart_irq_enable(uart, UART_IRQ_RX_CHAR, 1);
+ }
+
+ uart_reg_write(uart, AUTOBAUD_EN, 0x00); /* disable AUTOBAUD */
+ uart_reg_write(uart, EFR, 0x10); /* Enhanced Features Register */
+
+ /* no XON/XOFF flow control, ENHANCED_EN, no auto-RTS/CTS */
+ uart_reg_write(uart, EFR, (1 << 4));
+ /* enable Tx/Rx FIFO, Tx trigger at 56 spaces, Rx trigger at 60 chars */
+ //FIXME check those FIFO settings
+ uart_reg_write(uart, IIR, FIFO_EN | RX_FIFO_CLEAR | TX_FIFO_CLEAR |
+ (3 << TX_FIFO_TRIG_SHIFT) | (1 << RX_FIFO_TRIG_SHIFT));
+
+ /* RBR interrupt only when TX FIFO and TX shift register are empty */
+ uart_reg_write(uart, SCR, (1 << 0));// | (1 << 3));
+
+ /* 8 bit, 1 stop bit, no parity, no break */
+ uart_reg_write(uart, LCR, 0x03);
+
+ uart_set_lcr7bit(uart, 0);
+}
+
+void uart_poll(uint8_t uart) {
+ if(uart == CONS_UART_NR) {
+ uart_irq_handler_cons(0);
+ } else {
+ uart_irq_handler_sercomm(0);
+ }
+}
+
+void uart_irq_enable(uint8_t uart, enum uart_irq irq, int on)
+{
+ uint8_t ier = uart_reg_read(uart, IER);
+ uint8_t mask = 0;
+
+ switch (irq) {
+ case UART_IRQ_TX_EMPTY:
+ mask = (1 << 1);
+ break;
+ case UART_IRQ_RX_CHAR:
+ mask = (1 << 0);
+ break;
+ }
+
+ if (on)
+ ier |= mask;
+ else
+ ier &= ~mask;
+
+ uart_reg_write(uart, IER, ier);
+}
+
+
+void uart_putchar_wait(uint8_t uart, int c)
+{
+ /* wait while TX FIFO indicates full */
+ while (~readb(UART_REG(uart, LSR)) & 0x20) { }
+
+ /* put character in TX FIFO */
+ writeb(c, UART_REG(uart, RBR));
+}
+
+int uart_putchar_nb(uint8_t uart, int c)
+{
+ /* if TX FIFO indicates full, abort */
+ if (~readb(UART_REG(uart, LSR)) & 0x20)
+ return 0;
+
+ writeb(c, UART_REG(uart, RBR));
+ return 1;
+}
+
+int uart_getchar_nb(uint8_t uart, uint8_t *ch)
+{
+ uint8_t lsr;
+
+ lsr = readb(UART_REG(uart, LSR));
+
+ /* something strange happened */
+ if (lsr & 0x02)
+ printf("LSR RX_OE\n");
+ if (lsr & 0x04)
+ printf("LSR RX_PE\n");
+ if (lsr & 0x08)
+ printf("LSR RX_FE\n");
+ if (lsr & 0x10)
+ printf("LSR RX_BI\n");
+ if (lsr & 0x80)
+ printf("LSR RX_FIFO_STS\n");
+
+ /* is the Rx FIFO empty? */
+ if (!(lsr & 0x01))
+ return 0;
+
+ *ch = readb(UART_REG(uart, RBR));
+ //printf("getchar_nb(%u) = %02x\n", uart, *ch);
+ return 1;
+}
+
+int uart_tx_busy(uint8_t uart)
+{
+ /* Check THRE bit (LSR[5]) to see if FIFO is full */
+ if (~readb(UART_REG(uart, LSR)) & 0x20)
+ return 1;
+ return 0;
+}
+
+#if 0
+/* 26MHz clock input (used when no PLL initialized directly after poweron) */
+static const uint16_t divider[] = {
+ [UART_38400] = 42,
+ [UART_57600] = 28,
+ [UART_115200] = 14,
+ [UART_230400] = 7,
+ [UART_460800] = 14, /* would need UART_REG(HIGHSPEED) = 1 or 2 */
+ [UART_921600] = 7, /* would need UART_REG(HIGHSPEED) = 2 */
+};
+#endif
+
+/* 52MHz clock input (after PLL init) */
+static const uint16_t divider[] = {
+ [UART_38400] = 85,
+ [UART_57600] = 56,
+ [UART_115200] = 28,
+ [UART_230400] = 14,
+ [UART_460800] = 7,
+ [UART_921600] = 7, /* would need UART_REG(HIGHSPEED) = 1 */
+};
+
+int uart_baudrate(uint8_t uart, enum uart_baudrate bdrt)
+{
+ uint16_t div;
+
+ if (bdrt > ARRAY_SIZE(divider))
+ return -1;
+
+ div = divider[bdrt];
+ uart_set_lcr7bit(uart, 1);
+ writeb(div & 0xff, UART_REG(uart, DLL));
+ writeb(div >> 8, UART_REG(uart, DLH));
+ uart_set_lcr7bit(uart, 0);
+
+ return 0;
+}
diff --git a/Src/osmocombb/src/target/firmware/board/mt62xx/init.c b/Src/osmocombb/src/target/firmware/board/mt62xx/init.c
new file mode 100644
index 0000000..3f68375
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/mt62xx/init.c
@@ -0,0 +1,139 @@
+/* Initialization for the MT62xx Basebands */
+
+/* (C) 2010 by Steve Markgraf <steve@steve-m.de>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include <debug.h>
+#include <ctors.h>
+#include <memory.h>
+#include <board.h>
+#include <keypad.h>
+#include <uart.h>
+#include <console.h>
+#include <delay.h>
+
+#include <flash/cfi_flash.h>
+
+#include <comm/sercomm.h>
+#include <comm/timer.h>
+
+#include <mtk/emi.h>
+#include <mtk/mt6235.h>
+#include <mtk/system.h>
+
+void pll_init(void)
+{
+ /* Power on PLL */
+ writew(0, MTK_PLL_PDN_CON);
+ writew(PLL_CLKSQ_DIV2_DSP | PLL_CLKSQ_DIV2_MCU, MTK_PLL_CLK_CON);
+
+ writew(PLL_RST, MTK_PLL_PLL);
+ writew(0, MTK_PLL_PLL);
+ delay_ms(1);
+
+ /* Turn on PLL for MCU, DSP and USB */
+ writew(PLL_MPLLSEL_PLL | PLL_DPLLSEL | PLL_UPLLSEL, MTK_PLL_PLL);
+
+ /*
+ * Setup MCU clock register:
+ * ARMCLK = 208MHz, AHBx4CLK = 52MHz, AHBx8CLK = 104MHz
+ * we have to write to the read-only part (EMICLK) as well, otherwise
+ * the EMI won't work! (datasheet lies)
+ */
+ writew(7 << MCUCLK_CON_AHBX8CLK_SHIFT |
+ 3 << MCUCLK_CON_AHBX4CLK_SHIFT |
+ 15 << MCUCLK_CON_ARMCLK_SHIFT |
+ 7 << MCUCLK_CON_EMICLK_SHIFT,
+ MTK_CONFG_MCUCLK_CON);
+}
+
+void memory_init(void)
+{
+ int i;
+
+ /* Initialization for Hynix RAM */
+
+ /* Configure DRAM controller */
+ writel(0x0001000e, MTK_EMI_GEND);
+ writel(0x00088a0a, MTK_EMI_GENA);
+ writel(0x00000280, MTK_EMI_GENB);
+ writel(0x52945294, MTK_EMI_GENC);
+ writel(0x1c016605, MTK_EMI_CONL);
+ writel(0x00002828, MTK_EMI_CONM);
+ writel(0x02334000, MTK_EMI_CONI);
+ writel(0x16c12212, MTK_EMI_CONJ);
+ writel(0x032d0000, MTK_EMI_CONK);
+
+ for (i = 0; i < 5; ++i) {
+ /* Setup five single bits, one by one for DRAM init */
+ writel((1 << (24 + i)) | (0x400013), MTK_EMI_CONN);
+ delay_ms(1);
+ writel(0x400013, MTK_EMI_CONN);
+ delay_ms(1);
+ }
+
+#if 0
+ /* Initialization for Toshiba RAM */
+
+ /* Configure DRAM controller */
+ writel(0x0001000E, MTK_EMI_GEND);
+ writel(0x00088E3A, MTK_EMI_GENA);
+ writel(0x000000C0, MTK_EMI_GENB);
+ writel(0x18C618C6, MTK_EMI_GENC);
+ writel(0x18007505, MTK_EMI_CONL);
+ writel(0x00002828, MTK_EMI_CONM);
+ writel(0x00332000, MTK_EMI_CONI);
+ writel(0x3CD24431, MTK_EMI_CONJ);
+ writel(0x02000000, MTK_EMI_CONK);
+
+ for (i = 0; i < 5; ++i) {
+ /* Setup five single bits, one by one for DRAM init */
+ writel((1 << (24 + i)) | (0x500013), MTK_EMI_CONN);
+ delay_ms(1);
+ writel(0x500013, MTK_EMI_CONN);
+ delay_ms(1);
+ }
+
+#endif
+}
+
+void board_init(void)
+{
+ /* powerup the baseband */
+ writew(POWERKEY1_MAGIC, MTK_RTC_POWERKEY1);
+ writew(POWERKEY2_MAGIC, MTK_RTC_POWERKEY2);
+ writew(BBPU_MAGIC | RTC_BBPU_WRITE_EN |
+ RTC_BBPU_BBPU | RTC_BBPU_AUTO,
+ MTK_RTC_BBPU);
+ writew(1, MTK_RTC_WRTGR);
+
+ /* disable watchdog timer */
+ writew(WDT_MODE_KEY, MTK_RGU_WDT_MODE);
+
+ pll_init();
+ memory_init();
+
+ /* Initialize UART without interrupts */
+ uart_init(SERCOMM_UART_NR, 0);
+ uart_baudrate(SERCOMM_UART_NR, UART_115200);
+}
diff --git a/Src/osmocombb/src/target/firmware/board/pirelli_dpl10/init.c b/Src/osmocombb/src/target/firmware/board/pirelli_dpl10/init.c
new file mode 100644
index 0000000..53fb257
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/pirelli_dpl10/init.c
@@ -0,0 +1,127 @@
+/* Initialization for the Pirelli DP-L10 */
+
+/* (C) 2010 by Harald Welte <laforge@gnumonks.org>
+ * (C) 2011 by Steve Markgraf <steve@steve-m.de>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include <debug.h>
+#include <ctors.h>
+#include <memory.h>
+#include <board.h>
+#include <keypad.h>
+#include <console.h>
+#include <flash/cfi_flash.h>
+
+#include <calypso/irq.h>
+#include <calypso/clock.h>
+#include <calypso/dma.h>
+#include <calypso/rtc.h>
+#include <calypso/timer.h>
+#include <uart.h>
+#include <calypso/backlight.h>
+
+#include <comm/sercomm.h>
+#include <comm/timer.h>
+
+#include <abb/twl3025.h>
+#include <rf/trf6151.h>
+#include <display.h>
+
+#define ARMIO_LATCH_OUT 0xfffe4802
+#define ASIC_CONF_REG 0xfffef008
+
+static void board_io_init(void)
+{
+ uint16_t reg;
+
+ reg = readw(ASIC_CONF_REG);
+ /* Set function pins to I2C Mode */
+ reg |= ((1 << 12) | (1 << 7)); /* SCL / SDA */
+ /* TWL3025: Set SPI+RIF RX clock to rising edge */
+ reg |= (1 << 13) | (1 << 14);
+ writew(reg, ASIC_CONF_REG);
+}
+
+void board_init(void)
+{
+ /* Configure the memory interface */
+ calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS2, 5, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS3, 5, CALYPSO_MEM_16bit, 1);
+ calypso_mem_cfg(CALYPSO_CS4, 0, CALYPSO_MEM_8bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS6, 0, CALYPSO_MEM_32bit, 1);
+ calypso_mem_cfg(CALYPSO_nCS7, 0, CALYPSO_MEM_32bit, 0);
+
+ /* Set VTCXO_DIV2 = 1, configure PLL for 104 MHz and give ARM half of that */
+ calypso_clock_set(2, CALYPSO_PLL13_104_MHZ, ARM_MCLK_DIV_2);
+
+ /* Configure the RHEA bridge with some sane default values */
+ calypso_rhea_cfg(0, 0, 0xff, 0, 1, 0, 0);
+
+ /* Initialize board-specific GPIO */
+ board_io_init();
+
+ /* Enable bootrom mapping to route exception vectors to RAM */
+ calypso_bootrom(1);
+ calypso_exceptions_install();
+
+ /* Initialize interrupt controller */
+ irq_init();
+
+ /* initialize MODEM UART to be used for sercomm*/
+ uart_init(SERCOMM_UART_NR, 1);
+ uart_baudrate(SERCOMM_UART_NR, UART_115200);
+
+ /* Initialize IRDA UART to be used for old-school console code.
+ * note: IRDA uart only accessible on C115 and C117 PCB */
+ uart_init(CONS_UART_NR, 1);
+ uart_baudrate(CONS_UART_NR, UART_115200);
+
+ /* Initialize hardware timers */
+ hwtimer_init();
+
+ /* Initialize DMA controller */
+ dma_init();
+
+ /* Initialize real time clock */
+ rtc_init();
+
+ /* Initialize system timers (uses hwtimer 2) */
+ timer_init();
+
+ /* Initialize LCD driver (uses I2C) and backlight */
+ display = &st7558_display;
+ display_init();
+ bl_mode_pwl(1);
+ bl_level(0);
+
+ /* Initialize keypad driver */
+ keypad_init(1);
+
+ /* Initialize ABB driver (uses SPI) */
+ twl3025_init();
+
+ /* enable LEDB driver of Iota for keypad backlight */
+ twl3025_reg_write(AUXLED, 0x02);
+}
diff --git a/Src/osmocombb/src/target/firmware/board/pirelli_dpl10/rf_power.c b/Src/osmocombb/src/target/firmware/board/pirelli_dpl10/rf_power.c
new file mode 100644
index 0000000..9b89847
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/pirelli_dpl10/rf_power.c
@@ -0,0 +1,63 @@
+/* Tx RF power calibration for the Pirelli DP-L10 */
+
+/* (C) 2010 by Harald Welte <laforge@gnumonks.org>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <stdint.h>
+#include <osmocom/core/utils.h>
+
+/* GSM900 ARFCN 33, Measurements by Steve Markgraf / May 2010 */
+/* FIXME those are from the Compal phones, do measurements with the DP-L10 */
+const int16_t dbm2apc_gsm900[] = {
+ [0] = 151,
+ [1] = 152,
+ [2] = 153,
+ [3] = 155,
+ [4] = 156,
+ [5] = 158,
+ [6] = 160,
+ [7] = 162,
+ [8] = 164,
+ [9] = 167,
+ [10] = 170,
+ [11] = 173,
+ [12] = 177,
+ [13] = 182,
+ [14] = 187,
+ [15] = 192,
+ [16] = 199,
+ [17] = 206,
+ [18] = 214,
+ [19] = 223,
+ [20] = 233,
+ [21] = 244,
+ [22] = 260,
+ [23] = 271,
+ [24] = 288,
+ [25] = 307,
+ [26] = 327,
+ [27] = 350,
+ [28] = 376,
+ [29] = 407,
+ [30] = 456,
+ [31] = 575,
+};
+
+const int dbm2apc_gsm900_max = ARRAY_SIZE(dbm2apc_gsm900) - 1;
diff --git a/Src/osmocombb/src/target/firmware/board/pirelli_dpl10/rffe_dpl10_triband.c b/Src/osmocombb/src/target/firmware/board/pirelli_dpl10/rffe_dpl10_triband.c
new file mode 100644
index 0000000..d4d1342
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/board/pirelli_dpl10/rffe_dpl10_triband.c
@@ -0,0 +1,136 @@
+#include <stdint.h>
+#include <stdio.h>
+
+#include <debug.h>
+#include <memory.h>
+#include <rffe.h>
+#include <calypso/tsp.h>
+#include <rf/trf6151.h>
+
+/* This is a value that has been measured on the C123 by Harald: 71dBm,
+ it is the difference between the input level at the antenna and what
+ the DSP reports, subtracted by the total gain of the TRF6151 */
+#define SYSTEM_INHERENT_GAIN 71
+
+/* describe how the RF frontend is wired on the Pirelli DP-L10 */
+
+#define RITA_RESET TSPACT(5) /* Reset of the Rita TRF6151 */
+#define PA_ENABLE TSPACT(0) /* Enable the Power Amplifier */
+#define GSM_TXEN TSPACT(3) /* PA GSM switch, low-active,
+ * 1 for DCS1800/PCS1900 TX */
+
+/* All VCn controls are high-active */
+#define ASM_VC1 TSPACT(4) /* VC1 PCS1900 RX */
+#define ASM_VC2 TSPACT(10) /* VC2 DCS1800/PCS1900 TX */
+#define ASM_VC3 TSPACT(11) /* VC3 GSM900 TX */
+
+#define IOTA_STROBE TSPEN(0) /* Strobe for the Iota TSP */
+#define RITA_STROBE TSPEN(1) /* Strobe for the Rita TSP */
+
+/* switch RF Frontend Mode */
+void rffe_mode(enum gsm_band band, int tx)
+{
+ uint16_t tspact = tsp_act_state();
+
+ /* First we mask off all bits from the state cache */
+ tspact &= ~(PA_ENABLE| GSM_TXEN);
+ tspact &= ~(ASM_VC1 | ASM_VC2 | ASM_VC3);
+
+ switch (band) {
+ case GSM_BAND_850:
+ case GSM_BAND_900:
+ case GSM_BAND_1800:
+ break;
+ case GSM_BAND_1900:
+ tspact |= ASM_VC1;
+ break;
+ default:
+ /* TODO return/signal error here */
+ break;
+ }
+
+#ifdef CONFIG_TX_ENABLE
+ /* Then we selectively set the bits on, if required */
+ if (tx) {
+ switch (band) {
+ case GSM_BAND_850:
+ case GSM_BAND_900:
+ tspact |= ASM_VC3;
+ break;
+ case GSM_BAND_1800:
+ case GSM_BAND_1900:
+ tspact |= GSM_TXEN;
+ tspact |= ASM_VC2;
+ break;
+ default:
+ break;
+ }
+ tspact |= PA_ENABLE;
+ }
+#endif /* TRANSMIT_SUPPORT */
+
+ tsp_act_update(tspact);
+}
+
+/* Returns RF wiring */
+uint32_t rffe_get_rx_ports(void)
+{
+ return (1 << PORT_LO) | (1 << PORT_DCS1800) | (1 << PORT_PCS1900);
+}
+
+uint32_t rffe_get_tx_ports(void)
+{
+ return (1 << PORT_LO) | (1 << PORT_HI);
+}
+
+
+#define MCU_SW_TRACE 0xfffef00e
+#define ARM_CONF_REG 0xfffef006
+#define ASIC_CONF_REG 0xfffef008
+
+void rffe_init(void)
+{
+ uint16_t reg;
+
+ reg = readw(ARM_CONF_REG);
+ reg &= ~ (1 << 7); /* TSPACT4 I/O function, not nRDYMEM */
+ writew(reg, ARM_CONF_REG);
+
+ reg = readw(ASIC_CONF_REG);
+ reg &= ~ (1 << 15); /* TSPACT5 I/O function, not DPLLCLK */
+ writew(reg, ASIC_CONF_REG);
+
+ reg = readw(MCU_SW_TRACE);
+ reg &= ~(1 << 3); /* TSPACT10 I/O function, not nWAIT(1) */
+ reg &= ~(1 << 2); /* TSPACT11 I/O function, not MCLK(1) */
+ writew(reg, MCU_SW_TRACE);
+
+ /* Configure the TSPEN which is connected to the TWL3025 */
+ tsp_setup(IOTA_STROBE, 1, 0, 0);
+
+ trf6151_init(RITA_STROBE, RITA_RESET);
+}
+
+uint8_t rffe_get_gain(void)
+{
+ return trf6151_get_gain();
+}
+
+void rffe_set_gain(uint8_t dbm)
+{
+ trf6151_set_gain(dbm);
+}
+
+const uint8_t system_inherent_gain = SYSTEM_INHERENT_GAIN;
+
+/* Given the expected input level of exp_inp dBm/8 and the target of target_bb
+ * dBm8, configure the RF Frontend with the respective gain */
+void rffe_compute_gain(int16_t exp_inp, int16_t target_bb)
+{
+ trf6151_compute_gain(exp_inp, target_bb);
+}
+
+void rffe_rx_win_ctrl(int16_t exp_inp, int16_t target_bb)
+{
+ /* FIXME */
+}