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-rw-r--r--Src/osmocombb/src/target/firmware/include/calypso/backlight.h10
-rw-r--r--Src/osmocombb/src/target/firmware/include/calypso/buzzer.h34
-rw-r--r--Src/osmocombb/src/target/firmware/include/calypso/clock.h67
-rw-r--r--Src/osmocombb/src/target/firmware/include/calypso/dma.h6
-rw-r--r--Src/osmocombb/src/target/firmware/include/calypso/dsp.h41
-rw-r--r--Src/osmocombb/src/target/firmware/include/calypso/dsp_api.h1560
-rw-r--r--Src/osmocombb/src/target/firmware/include/calypso/du.h32
-rw-r--r--Src/osmocombb/src/target/firmware/include/calypso/irq.h49
-rw-r--r--Src/osmocombb/src/target/firmware/include/calypso/l1_environment.h385
-rw-r--r--Src/osmocombb/src/target/firmware/include/calypso/misc.h8
-rw-r--r--Src/osmocombb/src/target/firmware/include/calypso/rtc.h6
-rwxr-xr-xSrc/osmocombb/src/target/firmware/include/calypso/sim.h191
-rw-r--r--Src/osmocombb/src/target/firmware/include/calypso/timer.h25
-rw-r--r--Src/osmocombb/src/target/firmware/include/calypso/tpu.h122
-rw-r--r--Src/osmocombb/src/target/firmware/include/calypso/tsp.h31
15 files changed, 2567 insertions, 0 deletions
diff --git a/Src/osmocombb/src/target/firmware/include/calypso/backlight.h b/Src/osmocombb/src/target/firmware/include/calypso/backlight.h
new file mode 100644
index 0000000..3a6abd5
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/include/calypso/backlight.h
@@ -0,0 +1,10 @@
+#ifndef _CAL_BACKLIGHT_H
+#define _CAL_BACKLIGHT_H
+
+/* Switch backlight to PWL mode (or back) */
+void bl_mode_pwl(int on);
+
+/* Set the backlight level */
+void bl_level(uint8_t level);
+
+#endif /* CAL_BACKLIGHT_H */
diff --git a/Src/osmocombb/src/target/firmware/include/calypso/buzzer.h b/Src/osmocombb/src/target/firmware/include/calypso/buzzer.h
new file mode 100644
index 0000000..dcfd3a3
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/include/calypso/buzzer.h
@@ -0,0 +1,34 @@
+#ifndef _CAL_BUZZER_H
+#define _CAL_BUZZER_H
+
+#define NOTE(n,oct) (n<<2 | (oct & 0x03))
+
+#define NOTE_E 0x00
+#define NOTE_DIS 0x01
+#define NOTE_D 0x02
+#define NOTE_CIS 0x03
+#define NOTE_C 0x04
+#define NOTE_H 0x05
+#define NOTE_AIS 0x06
+#define NOTE_A 0x07
+#define NOTE_GIS 0x08
+#define NOTE_G 0x09
+#define NOTE_FIS 0x0A
+#define NOTE_F 0x0B
+
+#define OCTAVE_5 OCTAVE(0x00)
+#define OCTAVE_4 OCTAVE(0x01)
+#define OCTAVE_3 OCTAVE(0x02)
+#define OCTAVE_2 OCTAVE(0x03)
+#define OCTAVE_1 OCTAVE(0x04)
+
+#define OCTAVE(m) (m>NOTE_C?m+1:m)
+
+/* Switch buzzer to PWT mode (or back) */
+void buzzer_mode_pwt(int on);
+/* Set the buzzer level */
+void buzzer_volume(uint8_t level);
+/* Set the buzzer note */
+void buzzer_note(uint8_t note);
+
+#endif /* _CAL_BUZZER_H */
diff --git a/Src/osmocombb/src/target/firmware/include/calypso/clock.h b/Src/osmocombb/src/target/firmware/include/calypso/clock.h
new file mode 100644
index 0000000..abcfde1
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/include/calypso/clock.h
@@ -0,0 +1,67 @@
+#ifndef _CALYPSO_CLK_H
+#define _CALYPSO_CLK_H
+
+#include <stdint.h>
+
+#define CALYPSO_PLL26_52_MHZ ((2 << 8) | 0)
+#define CALYPSO_PLL26_86_7_MHZ ((10 << 8) | 2)
+#define CALYPSO_PLL26_87_MHZ ((3 << 8) | 0)
+#define CALYPSO_PLL13_104_MHZ ((8 << 8) | 0)
+
+enum mclk_div {
+ _ARM_MCLK_DIV_1 = 0,
+ ARM_MCLK_DIV_1 = 1,
+ ARM_MCLK_DIV_2 = 2,
+ ARM_MCLK_DIV_3 = 3,
+ ARM_MCLK_DIV_4 = 4,
+ ARM_MCLK_DIV_5 = 5,
+ ARM_MCLK_DIV_6 = 6,
+ ARM_MCLK_DIV_7 = 7,
+ ARM_MCLK_DIV_1_5 = 0x80 | 1,
+ ARM_MCLK_DIV_2_5 = 0x80 | 2,
+};
+
+void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div);
+void calypso_pll_set(uint16_t inp);
+void calypso_clk_dump(void);
+
+/* CNTL_RST */
+enum calypso_rst {
+ RESET_DSP = (1 << 1),
+ RESET_EXT = (1 << 2),
+ RESET_WDOG = (1 << 3),
+};
+
+void calypso_reset_set(enum calypso_rst calypso_rst, int active);
+int calypso_reset_get(enum calypso_rst);
+
+enum calypso_bank {
+ CALYPSO_nCS0 = 0,
+ CALYPSO_nCS1 = 2,
+ CALYPSO_nCS2 = 4,
+ CALYPSO_nCS3 = 6,
+ CALYPSO_nCS7 = 8,
+ CALYPSO_CS4 = 0xa,
+ CALYPSO_nCS6 = 0xc,
+};
+
+enum calypso_mem_width {
+ CALYPSO_MEM_8bit = 0,
+ CALYPSO_MEM_16bit = 1,
+ CALYPSO_MEM_32bit = 2,
+};
+
+void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws,
+ enum calypso_mem_width width, int we);
+
+/* Enable or disable the internal bootrom mapped to 0x0000'0000 */
+void calypso_bootrom(int enable);
+
+/* Enable or disable the debug unit */
+void calypso_debugunit(int enable);
+
+/* configure the RHEA bus bridge[s] */
+void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout,
+ uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1);
+
+#endif /* _CALYPSO_CLK_H */
diff --git a/Src/osmocombb/src/target/firmware/include/calypso/dma.h b/Src/osmocombb/src/target/firmware/include/calypso/dma.h
new file mode 100644
index 0000000..00b9bde
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/include/calypso/dma.h
@@ -0,0 +1,6 @@
+#ifndef _CALYPSO_DMA_H
+#define _CALYPSO_DMA_H
+
+void dma_init(void);
+
+#endif /* _CALYPSO_DMA_H */
diff --git a/Src/osmocombb/src/target/firmware/include/calypso/dsp.h b/Src/osmocombb/src/target/firmware/include/calypso/dsp.h
new file mode 100644
index 0000000..e4801cb
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/include/calypso/dsp.h
@@ -0,0 +1,41 @@
+#ifndef _CALYPSO_DSP_H
+#define _CALYPSO_DSP_H
+
+#include <calypso/dsp_api.h>
+
+#define CAL_DSP_TGT_BB_LVL 80
+
+struct gsm_time;
+
+struct dsp_api {
+ T_NDB_MCU_DSP *ndb;
+ T_DB_DSP_TO_MCU *db_r;
+ T_DB_MCU_TO_DSP *db_w;
+ T_PARAM_MCU_DSP *param;
+ int r_page;
+ int w_page;
+ int r_page_used;
+ int frame_ctr;
+};
+
+extern struct dsp_api dsp_api;
+
+void dsp_power_on(void);
+void dsp_dump_version(void);
+void dsp_dump(void);
+void dsp_checksum_task(void);
+void dsp_api_memset(uint16_t *ptr, int octets);
+void dsp_memcpy_to_api(volatile uint16_t *dsp_buf, const uint8_t *mcu_buf, int n, int be);
+void dsp_memcpy_from_api(uint8_t *mcu_buf, const volatile uint16_t *dsp_buf, int n, int be);
+void dsp_load_afc_dac(uint16_t afc);
+void dsp_load_apc_dac(uint16_t apc);
+void dsp_load_tch_param(struct gsm_time *next_time,
+ uint8_t chan_mode, uint8_t chan_type, uint8_t chan_sub,
+ uint8_t tch_loop, uint8_t sync_tch, uint8_t tn);
+void dsp_load_ciph_param(int mode, uint8_t *key);
+void dsp_end_scenario(void);
+
+void dsp_load_rx_task(uint16_t task, uint8_t burst_id, uint8_t tsc);
+void dsp_load_tx_task(uint16_t task, uint8_t burst_id, uint8_t tsc);
+
+#endif
diff --git a/Src/osmocombb/src/target/firmware/include/calypso/dsp_api.h b/Src/osmocombb/src/target/firmware/include/calypso/dsp_api.h
new file mode 100644
index 0000000..f9751f3
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/include/calypso/dsp_api.h
@@ -0,0 +1,1560 @@
+#ifndef _CAL_DSP_API_H
+#define _CAL_DSP_API_H
+
+/* This is a header file with structures imported from the TSM30 source code (l1_defty.h)
+ *
+ * As this header file only is a list of definitions and data structures, it is
+ * not ocnsidered to be a copyrightable work itself.
+ *
+ * Nonetheless, it might be good to rewrite it (without ugly typedefs!) */
+
+#if(L1_DYN_DSP_DWNLD == 1)
+ #include "l1_dyn_dwl_defty.h"
+#endif
+
+/* Include a header file that defines everything this l1_defty.h needs */
+#include "l1_environment.h"
+
+#define BASE_API_NDB 0xFFD001A8L /* 268 words */
+#define BASE_API_PARAM 0xFFD00862L /* 57 words */
+#define BASE_API_R_PAGE_0 0xFFD00050L /* 20 words */
+#define BASE_API_R_PAGE_1 0xFFD00078L /* 20 words */
+#define BASE_API_W_PAGE_0 0xFFD00000L /* 20 words */
+#define BASE_API_W_PAGE_1 0xFFD00028L /* 20 words */
+
+
+/***********************************************************/
+/* */
+/* Data structure for global info components. */
+/* */
+/***********************************************************/
+
+typedef struct
+{
+ API d_task_d; // (0) Downlink task command.
+ API d_burst_d; // (1) Downlink burst identifier.
+ API d_task_u; // (2) Uplink task command.
+ API d_burst_u; // (3) Uplink burst identifier.
+ API d_task_md; // (4) Downlink Monitoring (FB/SB) command.
+#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
+ API d_background; // (5) Background tasks
+#else
+ API d_reserved; // (5) Reserved
+#endif
+ API d_debug; // (6) Debug/Acknowledge/general purpose word.
+ API d_task_ra; // (7) RA task command.
+ API d_fn; // (8) FN, in Rep. period and FN%104, used for TRAFFIC/TCH only.
+ // bit [0..7] -> b_fn_report, FN in the normalized reporting period.
+ // bit [8..15] -> b_fn_sid, FN % 104, used for SID positionning.
+ API d_ctrl_tch; // (9) Tch channel description.
+ // bit [0..3] -> b_chan_mode, channel mode.
+ // bit [4..5] -> b_chan_type, channel type.
+ // bit [6] -> reset SACCH
+ // bit [7] -> vocoder ON
+ // bit [8] -> b_sync_tch_ul, synchro. TCH/UL.
+ // bit [9] -> b_sync_tch_dl, synchro. TCH/DL.
+ // bit [10] -> b_stop_tch_ul, stop TCH/UL.
+ // bit [11] -> b_stop_tch_dl, stop TCH/DL.
+ // bit [12.13] -> b_tch_loop, tch loops A/B/C.
+ API hole; // (10) unused hole.
+
+#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+ API d_ctrl_abb; // (11) Bit field indicating the analog baseband register to send.
+ // bit [0] -> b_ramp: the ramp information(a_ramp[]) is located in NDB
+ // bit [1.2] -> unused
+ // bit [3] -> b_apcdel: delays-register in NDB
+ // bit [4] -> b_afc: freq control register in DB
+ // bit [5..15] -> unused
+#endif
+ API a_a5fn[2]; // (12..13) Encryption Frame number.
+ // word 0, bit [0..4] -> T2.
+ // word 0, bit [5..10] -> T3.
+ // word 1, bit [0..11] -> T1.
+ API d_power_ctl; // (14) Power level control.
+ API d_afc; // (15) AFC value (enabled by "b_afc" in "d_ctrl_TCM4400 or in d_ctrl_abb").
+ API d_ctrl_system; // (16) Controle Register for RESET/RESUME.
+ // bit [0..2] -> b_tsq, training sequence.
+ // bit [3] -> b_bcch_freq_ind, BCCH frequency indication.
+ // bit [15] -> b_task_abort, DSP task abort command.
+}
+T_DB_MCU_TO_DSP;
+
+typedef struct
+{
+ API d_task_d; // (0) Downlink task command.
+ API d_burst_d; // (1) Downlink burst identifier.
+ API d_task_u; // (2) Uplink task command.
+ API d_burst_u; // (3) Uplink burst identifier.
+ API d_task_md; // (4) Downlink Monitoring (FB/SB) task command.
+#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
+ API d_background; // (5) Background tasks
+#else
+ API d_reserved; // (5) Reserved
+#endif
+ API d_debug; // (6) Debug/Acknowledge/general purpose word.
+ API d_task_ra; // (7) RA task command.
+
+#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
+ API a_serv_demod[4]; // ( 8..11) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR).
+ API a_pm[3]; // (12..14) Power measurement results, array of 3 words.
+ API a_sch[5]; // (15..19) Header + SB information, array of 5 words.
+#else
+ API a_pm[3]; // ( 8..10) Power measurement results, array of 3 words.
+ API a_serv_demod[4]; // (11..14) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR).
+ API a_sch[5]; // (15..19) Header + SB information, array of 5 words.
+#endif
+}
+T_DB_DSP_TO_MCU;
+
+#if (DSP == 34) || (DSP == 35) || (DSP == 36) // NDB GSM
+ typedef struct
+ {
+ // MISC Tasks
+ API d_dsp_page;
+
+ // DSP status returned (DSP --> MCU).
+ API d_error_status;
+
+ // RIF control (MCU -> DSP).
+ API d_spcx_rif;
+
+ API d_tch_mode; // TCH mode register.
+ // bit [0..1] -> b_dai_mode.
+ // bit [2] -> b_dtx.
+
+ API d_debug1; // bit 0 at 1 enable dsp f_tx delay for Omega
+
+ API d_dsp_test;
+
+ // Words dedicated to Software version (DSP code + Patch)
+ API d_version_number1;
+ API d_version_number2;
+
+ API d_debug_ptr;
+ API d_debug_bk;
+
+ API d_pll_config;
+
+ // GSM/GPRS DSP Debug trace support
+ API p_debug_buffer;
+ API d_debug_buffer_size;
+ API d_debug_trace_type;
+
+ #if (W_A_DSP_IDLE3 == 1)
+ // DSP report its state: 0 run, 1 Idle1, 2 Idle2, 3 Idle3.
+ API d_dsp_state;
+ // 5 words are reserved for any possible mapping modification
+ API d_hole1_ndb[2];
+ #else
+ // 6 words are reserved for any possible mapping modification
+ API d_hole1_ndb[3];
+ #endif
+
+ #if (AMR == 1)
+ API p_debug_amr;
+ #else
+ API d_hole_debug_amr;
+ #endif
+
+ #if (CHIPSET == 12)
+ #if (DSP == 35) || (DSP == 36)
+ API d_hole2_ndb[1];
+ API d_mcsi_select;
+ #else
+ API d_hole2_ndb[2];
+ #endif
+ #else
+ API d_hole2_ndb[2];
+ #endif
+
+ // New words APCDEL1 and APCDEL2 for 2TX: TX/PRACH combinations
+ API d_apcdel1_bis;
+ API d_apcdel2_bis;
+
+
+ // New registers due to IOTA analog base band
+ API d_apcdel2;
+ API d_vbctrl2;
+ API d_bulgcal;
+
+ // Analog Based Band
+ API d_afcctladd;
+
+ API d_vbuctrl;
+ API d_vbdctrl;
+ API d_apcdel1;
+ API d_apcoff;
+ API d_bulioff;
+ API d_bulqoff;
+ API d_dai_onoff;
+ API d_auxdac;
+
+ #if (ANLG_FAM == 1)
+ API d_vbctrl;
+ #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
+ API d_vbctrl1;
+ #endif
+
+ API d_bbctrl;
+
+ // Monitoring tasks control (MCU <- DSP)
+ // FB task
+ API d_fb_det; // FB detection result. (1 for FOUND).
+ API d_fb_mode; // Mode for FB detection algorithm.
+ API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
+
+ // SB Task
+ API a_sch26[5]; // Header + SB information, array of 5 words.
+
+ API d_audio_gain_ul;
+ API d_audio_gain_dl;
+
+ // Controller of the melody E2 audio compressor
+ API d_audio_compressor_ctrl;
+
+ // AUDIO module
+ API d_audio_init;
+ API d_audio_status;
+
+ // Audio tasks
+ // TONES (MCU -> DSP)
+ API d_toneskb_init;
+ API d_toneskb_status;
+ API d_k_x1_t0;
+ API d_k_x1_t1;
+ API d_k_x1_t2;
+ API d_pe_rep;
+ API d_pe_off;
+ API d_se_off;
+ API d_bu_off;
+ API d_t0_on;
+ API d_t0_off;
+ API d_t1_on;
+ API d_t1_off;
+ API d_t2_on;
+ API d_t2_off;
+ API d_k_x1_kt0;
+ API d_k_x1_kt1;
+ API d_dur_kb;
+ API d_shiftdl;
+ API d_shiftul;
+
+ API d_aec_ctrl;
+
+ API d_es_level_api;
+ API d_mu_api;
+
+ // Melody Ringer module
+ API d_melo_osc_used;
+ API d_melo_osc_active;
+ API a_melo_note0[4];
+ API a_melo_note1[4];
+ API a_melo_note2[4];
+ API a_melo_note3[4];
+ API a_melo_note4[4];
+ API a_melo_note5[4];
+ API a_melo_note6[4];
+ API a_melo_note7[4];
+
+ // selection of the melody format
+ API d_melody_selection;
+
+ // Holes due to the format melody E1
+ API a_melo_holes[3];
+
+ // Speech Recognition module
+ API d_sr_status; // status of the DSP speech reco task
+ API d_sr_param; // paramters for the DSP speech reco task: OOV threshold.
+ API d_sr_bit_exact_test; // bit exact test
+ API d_sr_nb_words; // number of words used in the speech recognition task
+ API d_sr_db_level; // estimate voice level in dB
+ API d_sr_db_noise; // estimate noise in dB
+ API d_sr_mod_size; // size of the model
+ API a_n_best_words[4]; // array of the 4 best words
+ API a_n_best_score[8]; // array of the 4 best scores (each score is 32 bits length)
+
+ // Audio buffer
+ API a_dd_1[22]; // Header + DATA traffic downlink information, sub. chan. 1.
+ API a_du_1[22]; // Header + DATA traffic uplink information, sub. chan. 1.
+
+ // V42bis module
+ API d_v42b_nego0;
+ API d_v42b_nego1;
+ API d_v42b_control;
+ API d_v42b_ratio_ind;
+ API d_mcu_control;
+ API d_mcu_control_sema;
+
+ // Background tasks
+ API d_background_enable;
+ API d_background_abort;
+ API d_background_state;
+ API d_max_background;
+ API a_background_tasks[16];
+ API a_back_task_io[16];
+
+ // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory)
+ API d_gea_mode_ovly;
+ API a_gea_kc_ovly[4];
+
+#if (ANLG_FAM == 3)
+ // SYREN specific registers
+ API d_vbpop;
+ API d_vau_delay_init;
+ API d_vaud_cfg;
+ API d_vauo_onoff;
+ API d_vaus_vol;
+ API d_vaud_pll;
+ API d_hole3_ndb[1];
+#elif ((ANLG_FAM == 1) || (ANLG_FAM == 2))
+
+ API d_hole3_ndb[7];
+
+#endif
+
+ // word used for the init of USF threshold
+ API d_thr_usf_detect;
+
+ // Encryption module
+ API d_a5mode; // Encryption Mode.
+
+ API d_sched_mode_gprs_ovly;
+
+ // 7 words are reserved for any possible mapping modification
+ API d_hole4_ndb[5];
+
+ // Ramp definition for Omega device
+ API a_ramp[16];
+
+ // CCCH/SACCH downlink information...(!!)
+ API a_cd[15]; // Header + CCCH/SACCH downlink information.
+
+ // FACCH downlink information........(!!)
+ API a_fd[15]; // Header + FACCH downlink information.
+
+ // Traffic downlink data frames......(!!)
+ API a_dd_0[22]; // Header + DATA traffic downlink information, sub. chan. 0.
+
+ // CCCH/SACCH uplink information.....(!!)
+ API a_cu[15]; // Header + CCCH/SACCH uplink information.
+
+ // FACCH downlink information........(!!)
+ API a_fu[15]; // Header + FACCH uplink information
+
+ // Traffic downlink data frames......(!!)
+ API a_du_0[22]; // Header + DATA traffic uplink information, sub. chan. 0.
+
+ // Random access.....................(MCU -> DSP).
+ API d_rach; // RACH information.
+
+ //...................................(MCU -> DSP).
+ API a_kc[4]; // Encryption Key Code.
+
+ // Integrated Data Services module
+ API d_ra_conf;
+ API d_ra_act;
+ API d_ra_test;
+ API d_ra_statu;
+ API d_ra_statd;
+ API d_fax;
+ API a_data_buf_ul[21];
+ API a_data_buf_dl[37];
+
+ // GTT API mapping for DSP code 34 (for test only)
+ #if (L1_GTT == 1)
+ API d_tty_status;
+ API d_tty_detect_thres;
+ API d_ctm_detect_shift;
+ API d_tty_fa_thres;
+ API d_tty_mod_norm;
+ API d_tty_reset_buffer_ul;
+ API d_tty_loop_ctrl;
+ API p_tty_loop_buffer;
+ #else
+ API a_tty_holes[8];
+ #endif
+
+ API a_sr_holes0[414];
+
+ #if (L1_NEW_AEC)
+ // new AEC
+ API d_cont_filter;
+ API d_granularity_att;
+ API d_coef_smooth;
+ API d_es_level_max;
+ API d_fact_vad;
+ API d_thrs_abs;
+ API d_fact_asd_fil;
+ API d_fact_asd_mut;
+ API d_far_end_pow_h;
+ API d_far_end_pow_l;
+ API d_far_end_noise_h;
+ API d_far_end_noise_l;
+ #else
+ API a_new_aec_holes[12];
+ #endif // L1_NEW_AEC
+
+ // Speech recognition model
+ API a_sr_holes1[145];
+ API d_cport_init;
+ API d_cport_ctrl;
+ API a_cport_cfr[2];
+ API d_cport_tcl_tadt;
+ API d_cport_tdat;
+ API d_cport_tvs;
+ API d_cport_status;
+ API d_cport_reg_value;
+
+ API a_cport_holes[1011];
+
+ API a_model[1041];
+
+ // EOTD buffer
+#if (L1_EOTD==1)
+ API d_eotd_first;
+ API d_eotd_max;
+ API d_eotd_nrj_high;
+ API d_eotd_nrj_low;
+ API a_eotd_crosscor[18];
+#else
+ API a_eotd_holes[22];
+#endif
+ // AMR ver 1.0 buffers
+ API a_amr_config[4];
+ API a_ratscch_ul[6];
+ API a_ratscch_dl[6];
+ API d_amr_snr_est; // estimation of the SNR of the AMR speech block
+ #if (L1_VOICE_MEMO_AMR)
+ API d_amms_ul_voc;
+ #else
+ API a_voice_memo_amr_holes[1];
+ #endif
+ API d_thr_onset_afs; // thresh detection ONSET AFS
+ API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS
+ API d_thr_ratscch_afs; // thresh detection RATSCCH AFS
+ API d_thr_update_afs; // thresh detection SID_UPDATE AFS
+ API d_thr_onset_ahs; // thresh detection ONSET AHS
+ API d_thr_sid_ahs; // thresh detection SID frames AHS
+ API d_thr_ratscch_marker;// thresh detection RATSCCH MARKER
+ API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA
+ API d_thr_soft_bits;
+ #if (MELODY_E2)
+ API d_melody_e2_osc_stop;
+ API d_melody_e2_osc_active;
+ API d_melody_e2_semaphore;
+ API a_melody_e2_osc[16][3];
+ API d_melody_e2_globaltimefactor;
+ API a_melody_e2_instrument_ptr[8];
+ API d_melody_e2_deltatime;
+
+ #if (AMR_THRESHOLDS_WORKAROUND)
+ API a_d_macc_thr_afs[8];
+ API a_d_macc_thr_ahs[6];
+ #else
+ API a_melody_e2_holes0[14];
+ #endif
+
+ API a_melody_e2_holes1[693];
+ API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE];
+ API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT];
+ #else
+ API d_holes[61];
+ #if (AMR_THRESHOLDS_WORKAROUND)
+ API a_d_macc_thr_afs[8];
+ API a_d_macc_thr_ahs[6];
+ #endif
+ #endif
+
+ }
+ T_NDB_MCU_DSP;
+#elif (DSP == 33) // NDB GSM
+ typedef struct
+ {
+ // MISC Tasks
+ API d_dsp_page;
+
+ // DSP status returned (DSP --> MCU).
+ API d_error_status;
+
+ // RIF control (MCU -> DSP).
+ API d_spcx_rif;
+
+ API d_tch_mode; // TCH mode register.
+ // bit [0..1] -> b_dai_mode.
+ // bit [2] -> b_dtx.
+
+ API d_debug1; // bit 0 at 1 enable dsp f_tx delay for Omega
+
+ API d_dsp_test;
+
+ // Words dedicated to Software version (DSP code + Patch)
+ API d_version_number1;
+ API d_version_number2;
+
+ API d_debug_ptr;
+ API d_debug_bk;
+
+ API d_pll_config;
+
+ // GSM/GPRS DSP Debug trace support
+ API p_debug_buffer;
+ API d_debug_buffer_size;
+ API d_debug_trace_type;
+
+ #if (W_A_DSP_IDLE3 == 1)
+ // DSP report its state: 0 run, 1 Idle1, 2 Idle2, 3 Idle3.
+ API d_dsp_state;
+ // 10 words are reserved for any possible mapping modification
+ API d_hole1_ndb[5];
+ #else
+ // 11 words are reserved for any possible mapping modification
+ API d_hole1_ndb[6];
+ #endif
+
+ // New words APCDEL1 and APCDEL2 for 2TX: TX/PRACH combinations
+ API d_apcdel1_bis;
+ API d_apcdel2_bis;
+
+
+ // New registers due to IOTA analog base band
+ API d_apcdel2;
+ API d_vbctrl2;
+ API d_bulgcal;
+
+ // Analog Based Band
+ API d_afcctladd;
+
+ API d_vbuctrl;
+ API d_vbdctrl;
+ API d_apcdel1;
+ API d_apcoff;
+ API d_bulioff;
+ API d_bulqoff;
+ API d_dai_onoff;
+ API d_auxdac;
+
+ #if (ANLG_FAM == 1)
+ API d_vbctrl;
+ #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
+ API d_vbctrl1;
+ #endif
+
+ API d_bbctrl;
+
+ // Monitoring tasks control (MCU <- DSP)
+ // FB task
+ API d_fb_det; // FB detection result. (1 for FOUND).
+ API d_fb_mode; // Mode for FB detection algorithm.
+ API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
+
+ // SB Task
+ API a_sch26[5]; // Header + SB information, array of 5 words.
+
+ API d_audio_gain_ul;
+ API d_audio_gain_dl;
+
+ // Controller of the melody E2 audio compressor
+ API d_audio_compressor_ctrl;
+
+ // AUDIO module
+ API d_audio_init;
+ API d_audio_status;
+
+ // Audio tasks
+ // TONES (MCU -> DSP)
+ API d_toneskb_init;
+ API d_toneskb_status;
+ API d_k_x1_t0;
+ API d_k_x1_t1;
+ API d_k_x1_t2;
+ API d_pe_rep;
+ API d_pe_off;
+ API d_se_off;
+ API d_bu_off;
+ API d_t0_on;
+ API d_t0_off;
+ API d_t1_on;
+ API d_t1_off;
+ API d_t2_on;
+ API d_t2_off;
+ API d_k_x1_kt0;
+ API d_k_x1_kt1;
+ API d_dur_kb;
+ API d_shiftdl;
+ API d_shiftul;
+
+ API d_aec_ctrl;
+
+ API d_es_level_api;
+ API d_mu_api;
+
+ // Melody Ringer module
+ API d_melo_osc_used;
+ API d_melo_osc_active;
+ API a_melo_note0[4];
+ API a_melo_note1[4];
+ API a_melo_note2[4];
+ API a_melo_note3[4];
+ API a_melo_note4[4];
+ API a_melo_note5[4];
+ API a_melo_note6[4];
+ API a_melo_note7[4];
+
+ // selection of the melody format
+ API d_melody_selection;
+
+ // Holes due to the format melody E1
+ API a_melo_holes[3];
+
+ // Speech Recognition module
+ API d_sr_status; // status of the DSP speech reco task
+ API d_sr_param; // paramters for the DSP speech reco task: OOV threshold.
+ API d_sr_bit_exact_test; // bit exact test
+ API d_sr_nb_words; // number of words used in the speech recognition task
+ API d_sr_db_level; // estimate voice level in dB
+ API d_sr_db_noise; // estimate noise in dB
+ API d_sr_mod_size; // size of the model
+ API a_n_best_words[4]; // array of the 4 best words
+ API a_n_best_score[8]; // array of the 4 best scores (each score is 32 bits length)
+
+ // Audio buffer
+ API a_dd_1[22]; // Header + DATA traffic downlink information, sub. chan. 1.
+ API a_du_1[22]; // Header + DATA traffic uplink information, sub. chan. 1.
+
+ // V42bis module
+ API d_v42b_nego0;
+ API d_v42b_nego1;
+ API d_v42b_control;
+ API d_v42b_ratio_ind;
+ API d_mcu_control;
+ API d_mcu_control_sema;
+
+ // Background tasks
+ API d_background_enable;
+ API d_background_abort;
+ API d_background_state;
+ API d_max_background;
+ API a_background_tasks[16];
+ API a_back_task_io[16];
+
+ // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory)
+ API d_gea_mode_ovly;
+ API a_gea_kc_ovly[4];
+
+ API d_hole3_ndb[8];
+
+ // Encryption module
+ API d_a5mode; // Encryption Mode.
+
+ API d_sched_mode_gprs_ovly;
+
+ // 7 words are reserved for any possible mapping modification
+ API d_hole4_ndb[5];
+
+ // Ramp definition for Omega device
+ API a_ramp[16];
+
+ // CCCH/SACCH downlink information...(!!)
+ API a_cd[15]; // Header + CCCH/SACCH downlink information.
+
+ // FACCH downlink information........(!!)
+ API a_fd[15]; // Header + FACCH downlink information.
+
+ // Traffic downlink data frames......(!!)
+ API a_dd_0[22]; // Header + DATA traffic downlink information, sub. chan. 0.
+
+ // CCCH/SACCH uplink information.....(!!)
+ API a_cu[15]; // Header + CCCH/SACCH uplink information.
+
+ // FACCH downlink information........(!!)
+ API a_fu[15]; // Header + FACCH uplink information
+
+ // Traffic downlink data frames......(!!)
+ API a_du_0[22]; // Header + DATA traffic uplink information, sub. chan. 0.
+
+ // Random access.....................(MCU -> DSP).
+ API d_rach; // RACH information.
+
+ //...................................(MCU -> DSP).
+ API a_kc[4]; // Encryption Key Code.
+
+ // Integrated Data Services module
+ API d_ra_conf;
+ API d_ra_act;
+ API d_ra_test;
+ API d_ra_statu;
+ API d_ra_statd;
+ API d_fax;
+ API a_data_buf_ul[21];
+ API a_data_buf_dl[37];
+
+ #if (L1_NEW_AEC)
+ // new AEC
+ API a_new_aec_holes[422];
+ API d_cont_filter;
+ API d_granularity_att;
+ API d_coef_smooth;
+ API d_es_level_max;
+ API d_fact_vad;
+ API d_thrs_abs;
+ API d_fact_asd_fil;
+ API d_fact_asd_mut;
+ API d_far_end_pow_h;
+ API d_far_end_pow_l;
+ API d_far_end_noise_h;
+ API d_far_end_noise_l;
+ #endif
+
+ // Speech recognition model
+ #if (L1_NEW_AEC)
+ API a_sr_holes[1165];
+ #else
+ API a_sr_holes[1599];
+ #endif // L1_NEW_AEC
+ API a_model[1041];
+
+ // EOTD buffer
+ #if (L1_EOTD==1)
+ API d_eotd_first;
+ API d_eotd_max;
+ API d_eotd_nrj_high;
+ API d_eotd_nrj_low;
+ API a_eotd_crosscor[18];
+ #else
+ API a_eotd_holes[22];
+ #endif
+
+ #if (MELODY_E2)
+ API a_melody_e2_holes0[27];
+ API d_melody_e2_osc_used;
+ API d_melody_e2_osc_active;
+ API d_melody_e2_semaphore;
+ API a_melody_e2_osc[16][3];
+ API d_melody_e2_globaltimefactor;
+ API a_melody_e2_instrument_ptr[8];
+ API a_melody_e2_holes1[708];
+ API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE];
+ API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT];
+ #endif
+ }
+ T_NDB_MCU_DSP;
+
+#elif ((DSP == 32) || (DSP == 31))
+ typedef struct
+ {
+ // Monitoring tasks control..........(MCU <- DSP)
+ API d_fb_det; // FB detection result. (1 for FOUND).
+ API d_fb_mode; // Mode for FB detection algorithm.
+ API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
+
+ // CCCH/SACCH downlink information...(!!)
+ API a_cd[15]; // Header + CCCH/SACCH downlink information.
+
+ // FACCH downlink information........(!!)
+ API a_fd[15]; // Header + FACCH downlink information.
+
+ // Traffic downlink data frames......(!!)
+ API a_dd_0[22]; // Header + DATA traffic downlink information, sub. chan. 0.
+ API a_dd_1[22]; // Header + DATA traffic downlink information, sub. chan. 1.
+
+ // CCCH/SACCH uplink information.....(!!)
+ API a_cu[15]; // Header + CCCH/SACCH uplink information.
+
+ #if (SPEECH_RECO)
+ // FACCH downlink information........(!!)
+ API a_fu[3]; // Header + FACCH uplink information
+ // The size of this buffer is 15 word but some speech reco words
+ // are overlayer with this buffer. This is the reason why the size is 3 instead of 15.
+ API d_sr_status; // status of the DSP speech reco task
+ API d_sr_param; // paramters for the DSP speech reco task: OOV threshold.
+ API sr_hole1; // hole
+ API d_sr_bit_exact_test; // bit exact test
+ API d_sr_nb_words; // number of words used in the speech recognition task
+ API d_sr_db_level; // estimate voice level in dB
+ API d_sr_db_noise; // estimate noise in dB
+ API d_sr_mod_size; // size of the model
+ API sr_holes_1[4]; // hole
+ #else
+ // FACCH downlink information........(!!)
+ API a_fu[15]; // Header + FACCH uplink information
+ #endif
+
+ // Traffic uplink data frames........(!!)
+ API a_du_0[22]; // Header + DATA traffic uplink information, sub. chan. 0.
+ API a_du_1[22]; // Header + DATA traffic uplink information, sub. chan. 1.
+
+ // Random access.....................(MCU -> DSP).
+ API d_rach; // RACH information.
+
+ //...................................(MCU -> DSP).
+ API d_a5mode; // Encryption Mode.
+ API a_kc[4]; // Encryption Key Code.
+ API d_tch_mode; // TCH mode register.
+ // bit [0..1] -> b_dai_mode.
+ // bit [2] -> b_dtx.
+
+ // OMEGA...........................(MCU -> DSP).
+ #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
+ API a_ramp[16];
+ #if (MELODY_E1)
+ API d_melo_osc_used;
+ API d_melo_osc_active;
+ API a_melo_note0[4];
+ API a_melo_note1[4];
+ API a_melo_note2[4];
+ API a_melo_note3[4];
+ API a_melo_note4[4];
+ API a_melo_note5[4];
+ API a_melo_note6[4];
+ API a_melo_note7[4];
+ #if (DSP==31)
+ // selection of the melody format
+ API d_melody_selection;
+ API holes[9];
+ #else // DSP==32
+ API d_dco_type; // Tide
+ API p_start_IQ;
+ API d_level_off;
+ API d_dco_dbg;
+ API d_tide_resa;
+ API d_asynch_margin; // Perseus Asynch Audio Workaround
+ API hole[4];
+ #endif // DSP 32
+
+ #else // NO MELODY E1
+ #if (DSP==31)
+ // selection of the melody format
+ API d_melody_selection;
+ API holes[43]; // 43 unused holes.
+ #else // DSP==32
+ API holes[34]; // 34 unused holes.
+ API d_dco_type; // Tide
+ API p_start_IQ;
+ API d_level_off;
+ API d_dco_dbg;
+ API d_tide_resa;
+ API d_asynch_margin; // Perseus Asynch Audio Workaround
+ API hole[4];
+ #endif //DSP == 32
+ #endif // NO MELODY E1
+
+ API d_debug3;
+ API d_debug2;
+ API d_debug1; // bit 0 at 1 enable dsp f_tx delay for Omega
+ API d_afcctladd;
+ API d_vbuctrl;
+ API d_vbdctrl;
+ API d_apcdel1;
+ API d_aec_ctrl;
+ API d_apcoff;
+ API d_bulioff;
+ API d_bulqoff;
+ API d_dai_onoff;
+ API d_auxdac;
+
+ #if (ANLG_FAM == 1)
+ API d_vbctrl;
+ #elif (ANLG_FAM == 2)
+ API d_vbctrl1;
+ #endif
+
+ API d_bbctrl;
+ #else
+ #error DSPCODE not supported with given ANALOG
+ #endif //(ANALOG)1, 2
+ //...................................(MCU -> DSP).
+ API a_sch26[5]; // Header + SB information, array of 5 words.
+
+ // TONES.............................(MCU -> DSP)
+ API d_toneskb_init;
+ API d_toneskb_status;
+ API d_k_x1_t0;
+ API d_k_x1_t1;
+ API d_k_x1_t2;
+ API d_pe_rep;
+ API d_pe_off;
+ API d_se_off;
+ API d_bu_off;
+ API d_t0_on;
+ API d_t0_off;
+ API d_t1_on;
+ API d_t1_off;
+ API d_t2_on;
+ API d_t2_off;
+ API d_k_x1_kt0;
+ API d_k_x1_kt1;
+ API d_dur_kb;
+
+ // PLL...............................(MCU -> DSP).
+ API d_pll_clkmod1;
+ API d_pll_clkmod2;
+
+ // DSP status returned..........(DSP --> MCU).
+ API d_error_status;
+
+ // RIF control.......................(MCU -> DSP).
+ API d_spcx_rif;
+
+ API d_shiftdl;
+ API d_shiftul;
+
+ API p_saec_prog;
+ API p_aec_prog;
+ API p_spenh_prog;
+
+ API a_ovly[75];
+ API d_ra_conf;
+ API d_ra_act;
+ API d_ra_test;
+ API d_ra_statu;
+ API d_ra_statd;
+ API d_fax;
+ #if (SPEECH_RECO)
+ API a_data_buf_ul[3];
+ API a_n_best_words[4]; // array of the 4 best words
+ API a_n_best_score[8]; // array of the 4 best scores (each score is 32 bits length)
+ API sr_holes_2[6];
+ API a_data_buf_dl[37];
+
+ API a_hole[24];
+
+ API d_sched_mode_gprs_ovly;
+
+ API fir_holes1[384];
+ API a_fir31_uplink[31];
+ API a_fir31_downlink[31];
+ API d_audio_init;
+ API d_audio_status;
+
+ API a_model[1041]; // array of the speech reco model
+ #else
+ API a_data_buf_ul[21];
+ API a_data_buf_dl[37];
+
+ API a_hole[24];
+
+ API d_sched_mode_gprs_ovly;
+
+ API fir_holes1[384];
+ API a_fir31_uplink[31];
+ API a_fir31_downlink[31];
+ API d_audio_init;
+ API d_audio_status;
+
+#if (L1_EOTD ==1)
+ API a_eotd_hole[369];
+
+ API d_eotd_first;
+ API d_eotd_max;
+ API d_eotd_nrj_high;
+ API d_eotd_nrj_low;
+ API a_eotd_crosscor[18];
+#endif
+ #endif
+ }
+ T_NDB_MCU_DSP;
+
+
+#else // OTHER DSP CODE like 17
+
+typedef struct
+{
+ // Monitoring tasks control..........(MCU <- DSP)
+ API d_fb_det; // FB detection result. (1 for FOUND).
+ API d_fb_mode; // Mode for FB detection algorithm.
+ API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
+
+ // CCCH/SACCH downlink information...(!!)
+ API a_cd[15]; // Header + CCCH/SACCH downlink information.
+
+ // FACCH downlink information........(!!)
+ API a_fd[15]; // Header + FACCH downlink information.
+
+ // Traffic downlink data frames......(!!)
+ #if (DATA14_4 == 0)
+ API a_dd_0[20]; // Header + DATA traffic downlink information, sub. chan. 0.
+ API a_dd_1[20]; // Header + DATA traffic downlink information, sub. chan. 1.
+ #endif
+ #if (DATA14_4 == 1)
+ API a_dd_0[22]; // Header + DATA traffic downlink information, sub. chan. 0.
+ API a_dd_1[22]; // Header + DATA traffic downlink information, sub. chan. 1.
+ #endif
+
+ // CCCH/SACCH uplink information.....(!!)
+ API a_cu[15]; // Header + CCCH/SACCH uplink information.
+
+ #if (SPEECH_RECO)
+ // FACCH downlink information........(!!)
+ API a_fu[3]; // Header + FACCH uplink information
+ // The size of this buffer is 15 word but some speech reco words
+ // are overlayer with this buffer. This is the reason why the size is 3 instead of 15.
+ API d_sr_status; // status of the DSP speech reco task
+ API d_sr_param; // paramters for the DSP speech reco task: OOV threshold.
+ API sr_hole1; // hole
+ API d_sr_bit_exact_test; // bit exact test
+ API d_sr_nb_words; // number of words used in the speech recognition task
+ API d_sr_db_level; // estimate voice level in dB
+ API d_sr_db_noise; // estimate noise in dB
+ API d_sr_mod_size; // size of the model
+ API sr_holes_1[4]; // hole
+ #else
+ // FACCH downlink information........(!!)
+ API a_fu[15]; // Header + FACCH uplink information
+ #endif
+
+ // Traffic uplink data frames........(!!)
+ #if (DATA14_4 == 0)
+ API a_du_0[20]; // Header + DATA traffic uplink information, sub. chan. 0.
+ API a_du_1[20]; // Header + DATA traffic uplink information, sub. chan. 1.
+ #endif
+ #if (DATA14_4 == 1)
+ API a_du_0[22]; // Header + DATA traffic uplink information, sub. chan. 0.
+ API a_du_1[22]; // Header + DATA traffic uplink information, sub. chan. 1.
+ #endif
+
+ // Random access.....................(MCU -> DSP).
+ API d_rach; // RACH information.
+
+ //...................................(MCU -> DSP).
+ API d_a5mode; // Encryption Mode.
+ API a_kc[4]; // Encryption Key Code.
+ API d_tch_mode; // TCH mode register.
+ // bit [0..1] -> b_dai_mode.
+ // bit [2] -> b_dtx.
+
+ // OMEGA...........................(MCU -> DSP).
+
+#if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
+ API a_ramp[16];
+ #if (MELODY_E1)
+ API d_melo_osc_used;
+ API d_melo_osc_active;
+ API a_melo_note0[4];
+ API a_melo_note1[4];
+ API a_melo_note2[4];
+ API a_melo_note3[4];
+ API a_melo_note4[4];
+ API a_melo_note5[4];
+ API a_melo_note6[4];
+ API a_melo_note7[4];
+ #if (DSP == 17)
+ // selection of the melody format
+ API d_dco_type; // Tide
+ API p_start_IQ;
+ API d_level_off;
+ API d_dco_dbg;
+ API d_tide_resa;
+ API d_asynch_margin; // Perseus Asynch Audio Workaround
+ API hole[4];
+ #else
+ API d_melody_selection;
+ API holes[9];
+ #endif
+ #else // NO MELODY E1
+ // selection of the melody format
+ #if (DSP == 17)
+ API holes[34]; // 34 unused holes.
+ API d_dco_type; // Tide
+ API p_start_IQ;
+ API d_level_off;
+ API d_dco_dbg;
+ API d_tide_resa;
+ API d_asynch_margin; // Perseus Asynch Audio Workaround
+ API hole[4]
+ #else
+ // selection of the melody format
+ API d_melody_selection;
+ API holes[43]; // 43 unused holes.
+ #endif
+ #endif
+ API d_debug3;
+ API d_debug2;
+ API d_debug1; // bit 0 at 1 enable dsp f_tx delay for Omega
+ API d_afcctladd;
+ API d_vbuctrl;
+ API d_vbdctrl;
+ API d_apcdel1;
+ API d_aec_ctrl;
+ API d_apcoff;
+ API d_bulioff;
+ API d_bulqoff;
+ API d_dai_onoff;
+ API d_auxdac;
+ #if (ANLG_FAM == 1)
+ API d_vbctrl;
+ #elif (ANLG_FAM == 2)
+ API d_vbctrl1;
+ #endif
+ API d_bbctrl;
+
+ #else
+ #error DSPCODE not supported with given ANALOG
+ #endif //(ANALOG)1, 2
+ //...................................(MCU -> DSP).
+ API a_sch26[5]; // Header + SB information, array of 5 words.
+
+ // TONES.............................(MCU -> DSP)
+ API d_toneskb_init;
+ API d_toneskb_status;
+ API d_k_x1_t0;
+ API d_k_x1_t1;
+ API d_k_x1_t2;
+ API d_pe_rep;
+ API d_pe_off;
+ API d_se_off;
+ API d_bu_off;
+ API d_t0_on;
+ API d_t0_off;
+ API d_t1_on;
+ API d_t1_off;
+ API d_t2_on;
+ API d_t2_off;
+ API d_k_x1_kt0;
+ API d_k_x1_kt1;
+ API d_dur_kb;
+
+ // PLL...............................(MCU -> DSP).
+ API d_pll_clkmod1;
+ API d_pll_clkmod2;
+
+ // DSP status returned..........(DSP --> MCU).
+ API d_error_status;
+
+ // RIF control.......................(MCU -> DSP).
+ API d_spcx_rif;
+
+ API d_shiftdl;
+ API d_shiftul;
+
+ #if (AEC == 1)
+ // AEC control.......................(MCU -> DSP).
+ #if (VOC == FR_EFR)
+ API p_aec_init;
+ API p_aec_prog;
+ API p_spenh_init;
+ API p_spenh_prog;
+ #endif
+
+ #if (VOC == FR_HR_EFR)
+ API p_saec_prog;
+ API p_aec_prog;
+ API p_spenh_prog;
+ #endif
+ #endif
+
+ API a_ovly[75];
+ API d_ra_conf;
+ API d_ra_act;
+ API d_ra_test;
+ API d_ra_statu;
+ API d_ra_statd;
+ API d_fax;
+ #if (SPEECH_RECO)
+ API a_data_buf_ul[3];
+ API a_n_best_words[4]; // array of the 4 best words
+ API a_n_best_score[8]; // array of the 4 best scores (each score is 32 bits length)
+ API sr_holes_2[6];
+ API a_data_buf_dl[37];
+
+ API fir_holes1[409];
+ API a_fir31_uplink[31];
+ API a_fir31_downlink[31];
+ API d_audio_init;
+ API d_audio_status;
+ API a_model[1041]; // array of the speech reco model
+ #else
+ API a_data_buf_ul[21];
+ API a_data_buf_dl[37];
+
+ API fir_holes1[409];
+ API a_fir31_uplink[31];
+ API a_fir31_downlink[31];
+ API d_audio_init;
+ API d_audio_status;
+ #endif
+}
+T_NDB_MCU_DSP;
+#endif
+
+#if (DSP == 34) || (DSP == 35) || (DSP == 36)
+typedef struct
+{
+ API_SIGNED d_transfer_rate;
+
+ // Common GSM/GPRS
+ // These words specified the latencies to applies on some peripherics
+ API_SIGNED d_lat_mcu_bridge;
+ API_SIGNED d_lat_mcu_hom2sam;
+ API_SIGNED d_lat_mcu_bef_fast_access;
+ API_SIGNED d_lat_dsp_after_sam;
+
+ // DSP Start address
+ API_SIGNED d_gprs_install_address;
+
+ API_SIGNED d_misc_config;
+
+ API_SIGNED d_cn_sw_workaround;
+
+ API_SIGNED d_hole2_param[4];
+
+ //...................................Frequency Burst.
+ API_SIGNED d_fb_margin_beg;
+ API_SIGNED d_fb_margin_end;
+ API_SIGNED d_nsubb_idle;
+ API_SIGNED d_nsubb_dedic;
+ API_SIGNED d_fb_thr_det_iacq;
+ API_SIGNED d_fb_thr_det_track;
+ //...................................Demodulation.
+ API_SIGNED d_dc_off_thres;
+ API_SIGNED d_dummy_thres;
+ API_SIGNED d_dem_pond_gewl;
+ API_SIGNED d_dem_pond_red;
+
+ //...................................TCH Full Speech.
+ API_SIGNED d_maccthresh1;
+ API_SIGNED d_mldt;
+ API_SIGNED d_maccthresh;
+ API_SIGNED d_gu;
+ API_SIGNED d_go;
+ API_SIGNED d_attmax;
+ API_SIGNED d_sm;
+ API_SIGNED d_b;
+
+ // V42Bis module
+ API_SIGNED d_v42b_switch_hyst;
+ API_SIGNED d_v42b_switch_min;
+ API_SIGNED d_v42b_switch_max;
+ API_SIGNED d_v42b_reset_delay;
+
+ //...................................TCH Half Speech.
+ API_SIGNED d_ldT_hr;
+ API_SIGNED d_maccthresh_hr;
+ API_SIGNED d_maccthresh1_hr;
+ API_SIGNED d_gu_hr;
+ API_SIGNED d_go_hr;
+ API_SIGNED d_b_hr;
+ API_SIGNED d_sm_hr;
+ API_SIGNED d_attmax_hr;
+
+ //...................................TCH Enhanced FR Speech.
+ API_SIGNED c_mldt_efr;
+ API_SIGNED c_maccthresh_efr;
+ API_SIGNED c_maccthresh1_efr;
+ API_SIGNED c_gu_efr;
+ API_SIGNED c_go_efr;
+ API_SIGNED c_b_efr;
+ API_SIGNED c_sm_efr;
+ API_SIGNED c_attmax_efr;
+
+ //...................................CHED
+ API_SIGNED d_sd_min_thr_tchfs;
+ API_SIGNED d_ma_min_thr_tchfs;
+ API_SIGNED d_md_max_thr_tchfs;
+ API_SIGNED d_md1_max_thr_tchfs;
+
+ API_SIGNED d_sd_min_thr_tchhs;
+ API_SIGNED d_ma_min_thr_tchhs;
+ API_SIGNED d_sd_av_thr_tchhs;
+ API_SIGNED d_md_max_thr_tchhs;
+ API_SIGNED d_md1_max_thr_tchhs;
+
+ API_SIGNED d_sd_min_thr_tchefs;
+ API_SIGNED d_ma_min_thr_tchefs;
+ API_SIGNED d_md_max_thr_tchefs;
+ API_SIGNED d_md1_max_thr_tchefs;
+
+ API_SIGNED d_wed_fil_ini;
+ API_SIGNED d_wed_fil_tc;
+ API_SIGNED d_x_min;
+ API_SIGNED d_x_max;
+ API_SIGNED d_slope;
+ API_SIGNED d_y_min;
+ API_SIGNED d_y_max;
+ API_SIGNED d_wed_diff_threshold;
+ API_SIGNED d_mabfi_min_thr_tchhs;
+
+ // FACCH module
+ API_SIGNED d_facch_thr;
+
+ // IDS module
+ API_SIGNED d_max_ovsp_ul;
+ API_SIGNED d_sync_thres;
+ API_SIGNED d_idle_thres;
+ API_SIGNED d_m1_thres;
+ API_SIGNED d_max_ovsp_dl;
+ API_SIGNED d_gsm_bgd_mgt;
+
+ // FIR coefficients
+ API a_fir_holes[4];
+ API a_fir31_uplink[31];
+ API a_fir31_downlink[31];
+}
+T_PARAM_MCU_DSP;
+#elif (DSP == 33)
+typedef struct
+{
+ API_SIGNED d_transfer_rate;
+
+ // Common GSM/GPRS
+ // These words specified the latencies to applies on some peripherics
+ API_SIGNED d_lat_mcu_bridge;
+ API_SIGNED d_lat_mcu_hom2sam;
+ API_SIGNED d_lat_mcu_bef_fast_access;
+ API_SIGNED d_lat_dsp_after_sam;
+
+ // DSP Start address
+ API_SIGNED d_gprs_install_address;
+
+ API_SIGNED d_misc_config;
+
+ API_SIGNED d_cn_sw_workaround;
+
+ #if DCO_ALGO
+ API_SIGNED d_cn_dco_param;
+
+ API_SIGNED d_hole2_param[3];
+ #else
+ API_SIGNED d_hole2_param[4];
+ #endif
+
+ //...................................Frequency Burst.
+ API_SIGNED d_fb_margin_beg;
+ API_SIGNED d_fb_margin_end;
+ API_SIGNED d_nsubb_idle;
+ API_SIGNED d_nsubb_dedic;
+ API_SIGNED d_fb_thr_det_iacq;
+ API_SIGNED d_fb_thr_det_track;
+ //...................................Demodulation.
+ API_SIGNED d_dc_off_thres;
+ API_SIGNED d_dummy_thres;
+ API_SIGNED d_dem_pond_gewl;
+ API_SIGNED d_dem_pond_red;
+
+ //...................................TCH Full Speech.
+ API_SIGNED d_maccthresh1;
+ API_SIGNED d_mldt;
+ API_SIGNED d_maccthresh;
+ API_SIGNED d_gu;
+ API_SIGNED d_go;
+ API_SIGNED d_attmax;
+ API_SIGNED d_sm;
+ API_SIGNED d_b;
+
+ // V42Bis module
+ API_SIGNED d_v42b_switch_hyst;
+ API_SIGNED d_v42b_switch_min;
+ API_SIGNED d_v42b_switch_max;
+ API_SIGNED d_v42b_reset_delay;
+
+ //...................................TCH Half Speech.
+ API_SIGNED d_ldT_hr;
+ API_SIGNED d_maccthresh_hr;
+ API_SIGNED d_maccthresh1_hr;
+ API_SIGNED d_gu_hr;
+ API_SIGNED d_go_hr;
+ API_SIGNED d_b_hr;
+ API_SIGNED d_sm_hr;
+ API_SIGNED d_attmax_hr;
+
+ //...................................TCH Enhanced FR Speech.
+ API_SIGNED c_mldt_efr;
+ API_SIGNED c_maccthresh_efr;
+ API_SIGNED c_maccthresh1_efr;
+ API_SIGNED c_gu_efr;
+ API_SIGNED c_go_efr;
+ API_SIGNED c_b_efr;
+ API_SIGNED c_sm_efr;
+ API_SIGNED c_attmax_efr;
+
+ //...................................CHED
+ API_SIGNED d_sd_min_thr_tchfs;
+ API_SIGNED d_ma_min_thr_tchfs;
+ API_SIGNED d_md_max_thr_tchfs;
+ API_SIGNED d_md1_max_thr_tchfs;
+
+ API_SIGNED d_sd_min_thr_tchhs;
+ API_SIGNED d_ma_min_thr_tchhs;
+ API_SIGNED d_sd_av_thr_tchhs;
+ API_SIGNED d_md_max_thr_tchhs;
+ API_SIGNED d_md1_max_thr_tchhs;
+
+ API_SIGNED d_sd_min_thr_tchefs;
+ API_SIGNED d_ma_min_thr_tchefs;
+ API_SIGNED d_md_max_thr_tchefs;
+ API_SIGNED d_md1_max_thr_tchefs;
+
+ API_SIGNED d_wed_fil_ini;
+ API_SIGNED d_wed_fil_tc;
+ API_SIGNED d_x_min;
+ API_SIGNED d_x_max;
+ API_SIGNED d_slope;
+ API_SIGNED d_y_min;
+ API_SIGNED d_y_max;
+ API_SIGNED d_wed_diff_threshold;
+ API_SIGNED d_mabfi_min_thr_tchhs;
+
+ // FACCH module
+ API_SIGNED d_facch_thr;
+
+ // IDS module
+ API_SIGNED d_max_ovsp_ul;
+ API_SIGNED d_sync_thres;
+ API_SIGNED d_idle_thres;
+ API_SIGNED d_m1_thres;
+ API_SIGNED d_max_ovsp_dl;
+ API_SIGNED d_gsm_bgd_mgt;
+
+ // FIR coefficients
+ API a_fir_holes[4];
+ API a_fir31_uplink[31];
+ API a_fir31_downlink[31];
+}
+T_PARAM_MCU_DSP;
+
+#else
+
+typedef struct
+{
+ //...................................Frequency Burst.
+ API_SIGNED d_nsubb_idle;
+ API_SIGNED d_nsubb_dedic;
+ API_SIGNED d_fb_thr_det_iacq;
+ API_SIGNED d_fb_thr_det_track;
+ //...................................Demodulation.
+ API_SIGNED d_dc_off_thres;
+ API_SIGNED d_dummy_thres;
+ API_SIGNED d_dem_pond_gewl;
+ API_SIGNED d_dem_pond_red;
+ API_SIGNED hole[1];
+ API_SIGNED d_transfer_rate;
+ //...................................TCH Full Speech.
+ API_SIGNED d_maccthresh1;
+ API_SIGNED d_mldt;
+ API_SIGNED d_maccthresh;
+ API_SIGNED d_gu;
+ API_SIGNED d_go;
+ API_SIGNED d_attmax;
+ API_SIGNED d_sm;
+ API_SIGNED d_b;
+
+ #if (VOC == FR_HR) || (VOC == FR_HR_EFR)
+ //...................................TCH Half Speech.
+ API_SIGNED d_ldT_hr;
+ API_SIGNED d_maccthresh_hr;
+ API_SIGNED d_maccthresh1_hr;
+ API_SIGNED d_gu_hr;
+ API_SIGNED d_go_hr;
+ API_SIGNED d_b_hr;
+ API_SIGNED d_sm_hr;
+ API_SIGNED d_attmax_hr;
+ #endif
+
+ #if (VOC == FR_EFR) || (VOC == FR_HR_EFR)
+ //...................................TCH Enhanced FR Speech.
+ API_SIGNED c_mldt_efr;
+ API_SIGNED c_maccthresh_efr;
+ API_SIGNED c_maccthresh1_efr;
+ API_SIGNED c_gu_efr;
+ API_SIGNED c_go_efr;
+ API_SIGNED c_b_efr;
+ API_SIGNED c_sm_efr;
+ API_SIGNED c_attmax_efr;
+ #endif
+
+ //...................................TCH Full Speech.
+ API_SIGNED d_sd_min_thr_tchfs;
+ API_SIGNED d_ma_min_thr_tchfs;
+ API_SIGNED d_md_max_thr_tchfs;
+ API_SIGNED d_md1_max_thr_tchfs;
+
+ #if (VOC == FR) || (VOC == FR_HR) || (VOC == FR_HR_EFR)
+ //...................................TCH Half Speech.
+ API_SIGNED d_sd_min_thr_tchhs;
+ API_SIGNED d_ma_min_thr_tchhs;
+ API_SIGNED d_sd_av_thr_tchhs;
+ API_SIGNED d_md_max_thr_tchhs;
+ API_SIGNED d_md1_max_thr_tchhs;
+ #endif
+
+ #if (VOC == FR_EFR) || (VOC == FR_HR_EFR)
+ //...................................TCH Enhanced FR Speech.
+ API_SIGNED d_sd_min_thr_tchefs; //(24L *C_POND_RED)
+ API_SIGNED d_ma_min_thr_tchefs; //(1200L *C_POND_RED)
+ API_SIGNED d_md_max_thr_tchefs; //(2000L *C_POND_RED)
+ API_SIGNED d_md1_max_thr_tchefs; //(160L *C_POND_RED)
+ API_SIGNED d_hole1;
+ #endif
+
+ API_SIGNED d_wed_fil_ini;
+ API_SIGNED d_wed_fil_tc;
+ API_SIGNED d_x_min;
+ API_SIGNED d_x_max;
+ API_SIGNED d_slope;
+ API_SIGNED d_y_min;
+ API_SIGNED d_y_max;
+ API_SIGNED d_wed_diff_threshold;
+ API_SIGNED d_mabfi_min_thr_tchhs;
+ API_SIGNED d_facch_thr;
+ API_SIGNED d_dsp_test;
+
+
+ #if (DATA14_4 == 0 ) || (VOC == FR_HR_EFR)
+ API_SIGNED d_patch_addr1;
+ API_SIGNED d_patch_data1;
+ API_SIGNED d_patch_addr2;
+ API_SIGNED d_patch_data2;
+ API_SIGNED d_patch_addr3;
+ API_SIGNED d_patch_data3;
+ API_SIGNED d_patch_addr4;
+ API_SIGNED d_patch_data4;
+ #endif
+
+ //...................................
+ API_SIGNED d_version_number; // DSP patch version
+ API_SIGNED d_ti_version; // customer number. No more used since 1.5
+
+ API_SIGNED d_dsp_page;
+
+ #if IDS
+ API_SIGNED d_max_ovsp_ul;
+ API_SIGNED d_sync_thres;
+ API_SIGNED d_idle_thres;
+ API_SIGNED d_m1_thres;
+ API_SIGNED d_max_ovsp_dl;
+ #endif
+
+
+}
+T_PARAM_MCU_DSP;
+#endif
+
+#if (DSP_DEBUG_TRACE_ENABLE == 1)
+typedef struct
+{
+ API d_debug_ptr_begin;
+ API d_debug_ptr_end;
+}
+T_DB2_DSP_TO_MCU;
+#endif
+
+/* DSP error as per ndb->d_error_status */
+enum dsp_error {
+ DSP_ERR_RHEA = 0x0001,
+ DSP_ERR_IQ_SAMPLES = 0x0004,
+ DSP_ERR_DMA_PROG = 0x0008,
+ DSP_ERR_DMA_TASK = 0x0010,
+ DSP_ERR_DMA_PEND = 0x0020,
+ DSP_ERR_VM = 0x0080,
+ DSP_ERR_DMA_UL_TASK = 0x0100,
+ DSP_ERR_DMA_UL_PROG = 0x0200,
+ DSP_ERR_DMA_UL_PEND = 0x0400,
+ DSP_ERR_STACK_OV = 0x0800,
+};
+
+/* How an ABB register + value is expressed in the API RAM */
+#define ABB_VAL(reg, val) ( (((reg) & 0x1F) << 1) | (((val) & 0x3FF) << 6) )
+
+/* How an ABB register + value | TRUE is expressed in the API RAM */
+#define ABB_VAL_T(reg, val) (ABB_VAL(reg, val) | 1)
+
+#endif /* _CAL_DSP_API_H */
diff --git a/Src/osmocombb/src/target/firmware/include/calypso/du.h b/Src/osmocombb/src/target/firmware/include/calypso/du.h
new file mode 100644
index 0000000..f2eae09
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/include/calypso/du.h
@@ -0,0 +1,32 @@
+/* Calypso DU (Debug Unit) Driver */
+
+/* (C) 2010 by Ingo Albrecht <prom@berlin.ccc.de>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef _CALYPSO_DU_H
+#define _CALYPSO_DU_H
+
+#include <calypso/clock.h>
+
+void calypso_du_init();
+void calypso_du_stop();
+void calypsu_du_dump();
+
+#endif /* _CALYPSO_DU_H */
diff --git a/Src/osmocombb/src/target/firmware/include/calypso/irq.h b/Src/osmocombb/src/target/firmware/include/calypso/irq.h
new file mode 100644
index 0000000..5ea5979
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/include/calypso/irq.h
@@ -0,0 +1,49 @@
+#ifndef _CALYPSO_IRQ_H
+#define _CALYPSO_IRQ_H
+
+enum irq_nr {
+ IRQ_WATCHDOG = 0,
+ IRQ_TIMER1 = 1,
+ IRQ_TIMER2 = 2,
+ IRQ_TSP_RX = 3,
+ IRQ_TPU_FRAME = 4,
+ IRQ_TPU_PAGE = 5,
+ IRQ_SIMCARD = 6,
+ IRQ_UART_MODEM = 7,
+ IRQ_KEYPAD_GPIO = 8,
+ IRQ_RTC_TIMER = 9,
+ IRQ_RTC_ALARM_I2C = 10,
+ IRQ_ULPD_GAUGING = 11,
+ IRQ_EXTERNAL = 12,
+ IRQ_SPI = 13,
+ IRQ_DMA = 14,
+ IRQ_API = 15,
+ IRQ_SIM_DETECT = 16,
+ IRQ_EXTERNAL_FIQ = 17,
+ IRQ_UART_IRDA = 18,
+ IRQ_ULPD_GSM_TIMER = 19,
+ IRQ_GEA = 20,
+ _NR_IRQ
+};
+
+typedef void irq_handler(enum irq_nr nr);
+
+/* initialize IRQ driver and enable interrupts */
+void irq_init(void);
+
+/* enable a certain interrupt */
+void irq_enable(enum irq_nr nr);
+
+/* disable a certain interrupt */
+void irq_disable(enum irq_nr nr);
+
+/* configure a certain interrupt */
+void irq_config(enum irq_nr nr, int fiq, int edge, int8_t prio);
+
+/* register an interrupt handler */
+void irq_register_handler(enum irq_nr nr, irq_handler *handler);
+
+/* Install the exception handlers to where the ROM loader jumps */
+void calypso_exceptions_install(void);
+
+#endif /* _CALYPSO_IRQ_H */
diff --git a/Src/osmocombb/src/target/firmware/include/calypso/l1_environment.h b/Src/osmocombb/src/target/firmware/include/calypso/l1_environment.h
new file mode 100644
index 0000000..d4d442c
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/include/calypso/l1_environment.h
@@ -0,0 +1,385 @@
+#include <stdint.h>
+
+typedef unsigned short API;
+typedef signed short API_SIGNED;
+
+#define FAR
+
+#define CHIPSET 12
+#define DSP 36
+#define ANLG_FAM 2 /* Iota */
+
+/* MFTAB */
+#define L1_MAX_FCT 5 /* Max number of fctions in a frame */
+#define MFTAB_SIZE 20
+
+#define NBMAX_CARRIER 174+374 /* Number of carriers (GSM-Ext + DCS */
+
+#define DPAGC_FIFO_LEN 4
+
+#define SIZE_HIST 10
+
+#if !L1_GPRS
+# define NBR_DL_L1S_TASKS 32
+#else
+# define NBR_DL_L1S_TASKS 45
+#endif
+
+#define NBR_L1A_PROCESSES 46
+
+#define W_A_DSP_IDLE3 1
+
+
+
+// Identifier for all DSP tasks.
+// ...RX & TX tasks identifiers.
+#define NO_DSP_TASK 0 // No task.
+#define NP_DSP_TASK 21 // Normal Paging reading task.
+#define EP_DSP_TASK 22 // Extended Paging reading task.
+#define NBS_DSP_TASK 19 // Normal BCCH serving reading task.
+#define EBS_DSP_TASK 20 // Extended BCCH serving reading task.
+#define NBN_DSP_TASK 17 // Normal BCCH neighbour reading task.
+#define EBN_DSP_TASK 18 // Extended BCCH neighbour reading task.
+#define ALLC_DSP_TASK 24 // CCCH reading task while performing FULL BCCH/CCCH reading task.
+#define CB_DSP_TASK 25 // CBCH reading task.
+#define DDL_DSP_TASK 26 // SDCCH/D (data) reading task.
+#define ADL_DSP_TASK 27 // SDCCH/A (SACCH) reading task.
+#define DUL_DSP_TASK 12 // SDCCH/D (data) transmit task.
+#define AUL_DSP_TASK 11 // SDCCH/A (SACCH) transmit task.
+#define RACH_DSP_TASK 10 // RACH transmit task.
+#define TCHT_DSP_TASK 13 // TCH Traffic data DSP task id (RX or TX)
+#define TCHA_DSP_TASK 14 // TCH SACCH data DSP task id (RX or TX)
+#define TCHD_DSP_TASK 28 // TCH Traffic data DSP task id (RX or TX)
+
+#define TCH_DTX_UL 15 // Replace UL task in DSP->MCU com. to say "burst not transmitted".
+
+#if (L1_GPRS)
+ // Identifier for DSP tasks Packet dedicated.
+ // ...RX & TX tasks identifiers.
+ //------------------------------------------------------------------------
+ // WARNING ... Need to aligned following macro with MCU/DSP GPRS Interface
+ //------------------------------------------------------------------------
+ #define PNP_DSP_TASK 30
+ #define PEP_DSP_TASK 31
+ #define PALLC_DSP_TASK 32
+ #define PBS_DSP_TASK 33
+
+ #define PTCCH_DSP_TASK 33
+
+#endif
+
+// Identifier for measurement, FB / SB search tasks.
+// Values 1,2,3 reserved for "number of measurements".
+#define FB_DSP_TASK 5 // Freq. Burst reading task in Idle mode.
+#define SB_DSP_TASK 6 // Sync. Burst reading task in Idle mode.
+#define TCH_FB_DSP_TASK 8 // Freq. Burst reading task in Dedicated mode.
+#define TCH_SB_DSP_TASK 9 // Sync. Burst reading task in Dedicated mode.
+#define IDLE1 1
+
+// Debug tasks
+#define CHECKSUM_DSP_TASK 33
+#define TST_NDB 35 // Checksum DSP->MCU
+#define TST_DB 36 // DB communication check
+#define INIT_VEGA 37
+#define DSP_LOOP_C 38
+
+// Identifier for measurement, FB / SB search tasks.
+// Values 1,2,3 reserved for "number of measurements".
+#define TCH_LOOP_A 31
+#define TCH_LOOP_B 32
+
+// bits in d_gsm_bgd_mgt - background task management
+#define B_DSPBGD_RECO 1 // start of reco in dsp background
+#define B_DSPBGD_UPD 2 // start of alignement update in dsp background
+#define B_DSPBGD_STOP_RECO 256 // stop of reco in dsp background
+#define B_DSPBGD_STOP_UPD 512 // stop of alignement update in dsp background
+
+// bit in d_pll_config
+#define B_32KHZ_CALIB (1 << 14) // force DSP in Idle1 during 32 khz calibration
+// ****************************************************************
+// NDB AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS
+// ****************************************************************
+// bits in d_tch_mode
+#define B_EOTD (1 << 0) // EOTD mode
+#define B_PLAY_UL (1 << 3) // Play UL
+#define B_DCO_ON (1 << 4) // DCO ON/OFF
+#define B_AUDIO_ASYNC (1 << 1) // WCP reserved
+
+// ****************************************************************
+// PARAMETER AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS
+// ****************************************************************
+#define C_POND_RED 1L
+// below values are defined in the file l1_time.h
+//#define D_NSUBB_IDLE 296L
+//#define D_NSUBB_DEDIC 30L
+#define D_FB_THR_DET_IACQ 0x3333L
+#define D_FB_THR_DET_TRACK 0x28f6L
+#define D_DC_OFF_THRES 0x7fffL
+#define D_DUMMY_THRES 17408L
+#define D_DEM_POND_GEWL 26624L
+#define D_DEM_POND_RED 20152L
+#define D_HOLE 0L
+#define D_TRANSFER_RATE 0x6666L
+
+// Full Rate vocoder definitions.
+#define D_MACCTHRESH1 7872L
+#define D_MLDT -4L
+#define D_MACCTHRESH 7872L
+#define D_GU 5772L
+#define D_GO 7872L
+#define D_ATTMAX 53L
+#define D_SM -892L
+#define D_B 208L
+#define D_SD_MIN_THR_TCHFS 15L //(24L *C_POND_RED)
+#define D_MA_MIN_THR_TCHFS 738L //(1200L *C_POND_RED)
+#define D_MD_MAX_THR_TCHFS 1700L //(2000L *C_POND_RED)
+#define D_MD1_MAX_THR_TCHFS 99L //(160L *C_POND_RED)
+
+#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
+ // Frequency burst definitions
+ #define D_FB_MARGIN_BEG 24
+ #define D_FB_MARGIN_END 22
+
+ // V42bis definitions
+ #define D_V42B_SWITCH_HYST 16L
+ #define D_V42B_SWITCH_MIN 64L
+ #define D_V42B_SWITCH_MAX 250L
+ #define D_V42B_RESET_DELAY 10L
+
+ // Latencies definitions
+ #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
+ // C.f. BUG1404
+ #define D_LAT_MCU_BRIDGE 0x000FL
+ #else
+ #define D_LAT_MCU_BRIDGE 0x0009L
+ #endif
+
+ #define D_LAT_MCU_HOM2SAM 0x000CL
+
+ #define D_LAT_MCU_BEF_FAST_ACCESS 0x0005L
+ #define D_LAT_DSP_AFTER_SAM 0x0004L
+
+ // Background Task in GSM mode: Initialization.
+ #define D_GSM_BGD_MGT 0L
+
+#if (CHIPSET == 4)
+ #define D_MISC_CONFIG 0L
+#elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
+ #define D_MISC_CONFIG 1L
+#else
+ #define D_MISC_CONFIG 0L
+#endif
+
+#endif
+
+// Hall Rate vocoder and ched definitions.
+
+#define D_SD_MIN_THR_TCHHS 37L
+#define D_MA_MIN_THR_TCHHS 344L
+#define D_MD_MAX_THR_TCHHS 2175L
+#define D_MD1_MAX_THR_TCHHS 138L
+#define D_SD_AV_THR_TCHHS 1845L
+#define D_WED_FIL_TC 0x7c00L
+#define D_WED_FIL_INI 4650L
+#define D_X_MIN 15L
+#define D_X_MAX 23L
+#define D_Y_MIN 703L
+#define D_Y_MAX 2460L
+#define D_SLOPE 135L
+#define D_WED_DIFF_THRESHOLD 406L
+#define D_MABFI_MIN_THR_TCHHS 5320L
+#define D_LDT_HR -5
+#define D_MACCTRESH_HR 6500
+#define D_MACCTRESH1_HR 6500
+#define D_GU_HR 2620
+#define D_GO_HR 3700
+#define D_B_HR 182
+#define D_SM_HR -1608
+#define D_ATTMAX_HR 53
+
+// Enhanced Full Rate vocoder and ched definitions.
+
+#define C_MLDT_EFR -4
+#define C_MACCTHRESH_EFR 8000
+#define C_MACCTHRESH1_EFR 8000
+#define C_GU_EFR 4522
+#define C_GO_EFR 6500
+#define C_B_EFR 174
+#define C_SM_EFR -878
+#define C_ATTMAX_EFR 53
+#define D_SD_MIN_THR_TCHEFS 15L //(24L *C_POND_RED)
+#define D_MA_MIN_THR_TCHEFS 738L //(1200L *C_POND_RED)
+#define D_MD_MAX_THR_TCHEFS 1230L //(2000L *C_POND_RED)
+#define D_MD1_MAX_THR_TCHEFS 99L //(160L *C_POND_RED)
+
+
+// Integrated Data Services definitions.
+#define D_MAX_OVSPD_UL 8
+// Detect frames containing 90% of 1s as synchro frames
+#define D_SYNC_THRES 0x3f50
+// IDLE frames are only frames with 100 % of 1s
+#define D_IDLE_THRES 0x4000
+#define D_M1_THRES 5
+#define D_MAX_OVSP_DL 8
+
+// d_ra_act: bit field definition
+#define B_F48BLK 5
+
+// Mask for b_itc information (d_ra_conf)
+#define CE_MASK 0x04
+
+#define D_FACCH_THR 0
+#define D_DSP_TEST 0
+#define D_VERSION_NUMBER 0
+#define D_TI_VERSION 0
+
+
+/*------------------------------------------------------------------------------*/
+/* */
+/* DEFINITIONS FOR DSP <-> MCU COMMUNICATION. */
+/* ++++++++++++++++++++++++++++++++++++++++++ */
+/* */
+/*------------------------------------------------------------------------------*/
+// COMMUNICATION Interrupt definition
+//------------------------------------
+#define ALL_16BIT 0xffffL
+#define B_GSM_PAGE (1 << 0)
+#define B_GSM_TASK (1 << 1)
+#define B_MISC_PAGE (1 << 2)
+#define B_MISC_TASK (1 << 3)
+
+#define B_GSM_PAGE_MASK (ALL_16BIT ^ B_GSM_PAGE)
+#define B_GSM_TASK_MASK (ALL_16BIT ^ B_GSM_TASK)
+#define B_MISC_PAGE_MASK (ALL_16BIT ^ B_MISC_PAGE)
+#define B_MISC_TASK_MASK (ALL_16BIT ^ B_MISC_TASK)
+
+// Common definition
+//----------------------------------
+// Index to *_DEMOD* arrays.
+#define D_TOA 0 // Time Of Arrival.
+#define D_PM 1 // Power Measurement.
+#define D_ANGLE 2 // Angle (AFC correction)
+#define D_SNR 3 // Signal / Noise Ratio.
+
+// Bit name/position definitions.
+#define B_FIRE0 5 // Fire result bit 0. (00 -> NO ERROR) (01 -> ERROR CORRECTED)
+#define B_FIRE1 6 // Fire result bit 1. (10 -> ERROR) (11 -> unused)
+#define B_SCH_CRC 8 // CRC result for SB decoding. (1 for ERROR).
+#define B_BLUD 15 // Uplink,Downlink data block Present. (1 for PRESENT).
+#define B_AF 14 // Activity bit: 1 if data block is valid.
+#define B_BFI 2 // Bad Frame Indicator
+#define B_UFI 0 // UNRELIABLE FRAME Indicator
+#define B_ECRC 9 // Enhanced full rate CRC bit
+#define B_EMPTY_BLOCK 10 // for voice memo purpose, this bit is used to determine
+
+#if (DEBUG_DEDIC_TCH_BLOCK_STAT == 1)
+ #define FACCH_GOOD 10
+ #define FACCH_BAD 11
+#endif
+
+#if (AMR == 1)
+ // Place of the RX type in the AMR block header
+ #define RX_TYPE_SHIFT 3
+ #define RX_TYPE_MASK 0x0038
+
+ // Place of the vocoder type in the AMR block header
+ #define VOCODER_TYPE_SHIFT 0
+ #define VOCODER_TYPE_MASK 0x0007
+
+ // List of the possible RX types in a_dd block
+ #define SPEECH_GOOD 0
+ #define SPEECH_DEGRADED 1
+ #define ONSET 2
+ #define SPEECH_BAD 3
+ #define SID_FIRST 4
+ #define SID_UPDATE 5
+ #define SID_BAD 6
+ #define AMR_NO_DATA 7
+ #define AMR_INHIBIT 8
+
+ // List of possible RX types in RATSCCH block
+ #define C_RATSCCH_GOOD 5
+
+ // List of the possible AMR channel rate
+ #define AMR_CHANNEL_4_75 0
+ #define AMR_CHANNEL_5_15 1
+ #define AMR_CHANNEL_5_9 2
+ #define AMR_CHANNEL_6_7 3
+ #define AMR_CHANNEL_7_4 4
+ #define AMR_CHANNEL_7_95 5
+ #define AMR_CHANNEL_10_2 6
+ #define AMR_CHANNEL_12_2 7
+
+ // Types of RATSCCH blocks
+ #define C_RATSCCH_UNKNOWN 0
+ #define C_RATSCCH_CMI_PHASE_REQ 1
+ #define C_RATSCCH_AMR_CONFIG_REQ_MAIN 2
+ #define C_RATSCCH_AMR_CONFIG_REQ_ALT 3
+ #define C_RATSCCH_AMR_CONFIG_REQ_ALT_IGNORE 4 // Alternative AMR_CONFIG_REQ with updates coming in the next THRES_REQ block
+ #define C_RATSCCH_THRES_REQ 5
+
+ // These flags define a bitmap that indicates which AMR parameters are being modified by a RATSCCH
+ #define C_AMR_CHANGE_CMIP 0
+ #define C_AMR_CHANGE_ACS 1
+ #define C_AMR_CHANGE_ICM 2
+ #define C_AMR_CHANGE_THR1 3
+ #define C_AMR_CHANGE_THR2 4
+ #define C_AMR_CHANGE_THR3 5
+ #define C_AMR_CHANGE_HYST1 6
+ #define C_AMR_CHANGE_HYST2 7
+ #define C_AMR_CHANGE_HYST3 8
+
+ // CMIP default value
+ #define C_AMR_CMIP_DEFAULT 1 // According to ETSI specification 05.09, cmip is always 1 by default (new channel, handover...)
+
+#endif
+// "d_ctrl_tch" bits positions for TCH configuration.
+#define B_CHAN_MODE 0
+#define B_CHAN_TYPE 4
+#define B_RESET_SACCH 6
+#define B_VOCODER_ON 7
+#define B_SYNC_TCH_UL 8
+#if (AMR == 1)
+ #define B_SYNC_AMR 9
+#else
+#define B_SYNC_TCH_DL 9
+#endif
+#define B_STOP_TCH_UL 10
+#define B_STOP_TCH_DL 11
+#define B_TCH_LOOP 12
+#define B_SUBCHANNEL 15
+
+// "d_ctrl_abb" bits positions for conditionnal loading of abb registers.
+#define B_RAMP 0
+#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+ #define B_BULRAMPDEL 3 // Note: this name is changed
+ #define B_BULRAMPDEL2 2 // Note: this name is changed
+ #define B_BULRAMPDEL_BIS 9
+ #define B_BULRAMPDEL2_BIS 10
+#endif
+#define B_AFC 4
+
+// "d_ctrl_system" bits positions.
+#define B_TSQ 0
+#define B_BCCH_FREQ_IND 3
+#define B_TASK_ABORT 15 // Abort RF tasks for DSP.
+
+/* Channel type definitions for DEDICATED mode */
+#define INVALID_CHANNEL 0
+#define TCH_F 1
+#define TCH_H 2
+#define SDCCH_4 3
+#define SDCCH_8 4
+
+/* Channel mode definitions for DEDICATED mode */
+#define SIG_ONLY_MODE 0 // signalling only
+#define TCH_FS_MODE 1 // speech full rate
+#define TCH_HS_MODE 2 // speech half rate
+#define TCH_96_MODE 3 // data 9,6 kb/s
+#define TCH_48F_MODE 4 // data 4,8 kb/s full rate
+#define TCH_48H_MODE 5 // data 4,8 kb/s half rate
+#define TCH_24F_MODE 6 // data 2,4 kb/s full rate
+#define TCH_24H_MODE 7 // data 2,4 kb/s half rate
+#define TCH_EFR_MODE 8 // enhanced full rate
+#define TCH_144_MODE 9 // data 14,4 kb/s half rate
+
diff --git a/Src/osmocombb/src/target/firmware/include/calypso/misc.h b/Src/osmocombb/src/target/firmware/include/calypso/misc.h
new file mode 100644
index 0000000..4e48093
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/include/calypso/misc.h
@@ -0,0 +1,8 @@
+#ifndef _CAL_MISC_H
+#define _CAL_MISC_H
+
+void memdump_range(unsigned int *ptr, unsigned int len);
+void dump_mem(void);
+void dump_dev_id(void);
+
+#endif /* _CAL_MISC_H */
diff --git a/Src/osmocombb/src/target/firmware/include/calypso/rtc.h b/Src/osmocombb/src/target/firmware/include/calypso/rtc.h
new file mode 100644
index 0000000..17528d0
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/include/calypso/rtc.h
@@ -0,0 +1,6 @@
+#ifndef _CALYPSO_RTC_H
+#define _CALYPSO_RTC_H
+
+void rtc_init(void);
+
+#endif /* _CALYPSO_RTC_H */
diff --git a/Src/osmocombb/src/target/firmware/include/calypso/sim.h b/Src/osmocombb/src/target/firmware/include/calypso/sim.h
new file mode 100755
index 0000000..b2a2164
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/include/calypso/sim.h
@@ -0,0 +1,191 @@
+/* Driver for Simcard Controller inside TI Calypso/Iota */
+
+/* (C) 2010 by Philipp Fabian Benedikt Maier <philipp-maier@runningserver.com>
+ *
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef _CALYPSO_SIM_H
+#define _CALYPSO_SIM_H
+
+/* == REGISTERS IN THE IOTA BASEBAND == */
+
+/* SimCard Control Register */
+#define VRPCSIM_SIMLEN (1 << 3) /* Enable level shifter */
+#define VRPCSIM_SIMRSU (1 << 2) /* voltage regulator output status */
+#define VRPCSIM_RSIMEN (1 << 1) /* Voltage regulator enable */
+#define VRPCSIM_SIMSEL 1 /* Select the VRSIM output voltage 1=2.9V, 0=1.8V */
+
+
+
+/* == REGISTERS IN THE CALYPSO CPU == */
+
+/* Reg_sim_cmd register (R/W) - FFFE:0000 */
+#define REG_SIM_CMD 0xFFFE0000 /* register address */
+#define REG_SIM_CMD_CMDCARDRST 1 /* SIM card reset sequence */
+#define REG_SIM_CMD_CMDIFRST (1 << 1) /* SIM interface software reset */
+#define REG_SIM_CMD_CMDSTOP (1 << 2) /* SIM card stop procedure */
+#define REG_SIM_CMD_CMDSTART (1 << 3) /* SIM card start procedure */
+#define REG_SIM_CMD_MODULE_CLK_EN (1 << 4) /* Clock of the module */
+
+/* Reg_sim_stat register (R) - FFFE:0002 */
+#define REG_SIM_STAT 0xFFFE0002 /* register address */
+#define REG_SIM_STAT_STATNOCARD 1 /* card presence, 0 = no card, 1 = card detected */
+#define REG_SIM_STAT_STATTXPAR (1 << 1) /* parity check for transmit byte, 0 = parity error, 1 = parity OK */
+#define REG_SIM_STAT_STATFIFOFULL (1 << 2) /* FIFO content, 1 = FIFO full */
+#define REG_SIM_STAT_STATFIFOEMPTY (1 << 3) /* FIFO content, 1 = FIFO empty */
+
+/* Reg_sim_conf1 register (R/W) - FFFE:0004 */
+#define REG_SIM_CONF1 0xFFFE0004 /* register address */
+#define REG_SIM_CONF1_CONFCHKPAR 1 /* enable parity check on reception */
+#define REG_SIM_CONF1_CONFCODCONV (1 << 1) /* coding convention: (TS character) */
+#define REG_SIM_CONF1_CONFTXRX (1 << 2) /* SIO line direction */
+#define REG_SIM_CONF1_CONFSCLKEN (1 << 3) /* SIM clock */
+#define REG_SIM_CONF1_reserved (1 << 4) /* ETU period */
+#define REG_SIM_CONF1_CONFSCLKDIV (1 << 5) /* SIM clock frequency */
+#define REG_SIM_CONF1_CONFSCLKLEV (1 << 6) /* SIM clock idle level */
+#define REG_SIM_CONF1_CONFETUPERIOD (1 << 7) /* ETU period */
+#define REG_SIM_CONF1_CONFBYPASS (1 << 8) /* bypass hardware timers and start and stop sequences */
+#define REG_SIM_CONF1_CONFSVCCLEV (1 << 9) /* logic level on SVCC (used if CONFBYPASS = 1) */
+#define REG_SIM_CONF1_CONFSRSTLEV (1 << 10) /* logic level on SRST (used if CONFBYPASS = 1) */
+#define REG_SIM_CONF1_CONFTRIG 11 /* FIFO trigger level */
+#define REG_SIM_CONF1_CONFTRIG_0 (1 << 11)
+#define REG_SIM_CONF1_CONFTRIG_1 (1 << 12)
+#define REG_SIM_CONF1_CONFTRIG_2 (1 << 13)
+#define REG_SIM_CONF1_CONFTRIG_3 (1 << 14)
+#define REG_SIM_CONF1_CONFTRIG_MASK 0xF
+#define REG_SIM_CONF1_CONFSIOLOW (1 << 15) /* SIO - 0 = no effect, 1 = force low */
+
+/* Reg_sim_conf2 register (R/W) - FFFE:0006 */
+#define REG_SIM_CONF2 0xFFFE0006 /* register address */
+#define REG_SIM_CONF2_CONFTFSIM 0 /* time delay for filtering of SIM_CD */
+#define REG_SIM_CONF2_CONFTFSIM_0 1 /* time-unit = 1024 * TCK13M (card extraction) */
+#define REG_SIM_CONF2_CONFTFSIM_1 (1 << 1) /* or */
+#define REG_SIM_CONF2_CONFTFSIM_2 (1 << 2) /* time-unit = 8192 * TCK13M (card insertion) */
+#define REG_SIM_CONF2_CONFTFSIM_3 (1 << 3)
+#define REG_SIM_CONF2_CONFTFSIM_MASK 0xF
+#define REG_SIM_CONF2_CONFTDSIM 4 /* time delay for contact activation/deactivation */
+#define REG_SIM_CONF2_CONFTDSIM_0 (1 << 4) /* time unit = 8 * TCKETU */
+#define REG_SIM_CONF2_CONFTDSIM_1 (1 << 5)
+#define REG_SIM_CONF2_CONFTDSIM_2 (1 << 6)
+#define REG_SIM_CONF2_CONFTDSIM_3 (1 << 7)
+#define REG_SIM_CONF2_CONFTDSIM_MASK 0xF
+#define REG_SIM_CONF2_CONFWAITI 8 /* CONFWAITI overflow wait time between two received */
+#define REG_SIM_CONF2_CONFWAITI_0 (1 << 8) /* character time unit = 960 *D * TCKETU */
+#define REG_SIM_CONF2_CONFWAITI_1 (1 << 9) /* with D parameter = 1 or 8 (TA1 character) */
+#define REG_SIM_CONF2_CONFWAITI_2 (1 << 10)
+#define REG_SIM_CONF2_CONFWAITI_3 (1 << 11)
+#define REG_SIM_CONF2_CONFWAITI_4 (1 << 12)
+#define REG_SIM_CONF2_CONFWAITI_5 (1 << 13)
+#define REG_SIM_CONF2_CONFWAITI_6 (1 << 14)
+#define REG_SIM_CONF2_CONFWAITI_7 (1 << 15)
+#define REG_SIM_CONF2_CONFWAITI_MASK 0xFF
+
+/* Reg_sim_it register (R) - FFFE:0008 */
+#define REG_SIM_IT 0xFFFE0008 /* register address */
+#define REG_SIM_IT_SIM_NATR 1 /* 0 = on read access to REG_SIM_IT, 1 = no answer to reset */
+#define REG_SIM_IT_SIM_WT (1 << 1) /* 0 = on read access to REG_SIM_IT, 1 = character underflow */
+#define REG_SIM_IT_SIM_OV (1 << 2) /* 0 = on read access to REG_SIM_IT, 1 = receive overflow */
+#define REG_SIM_IT_SIM_TX (1 << 3) /* 0 = on write access to REG_SIM_DTX or */
+ /* on switching from transmit to receive, mode (CONFTXRX bit) */
+ /* 1 = waiting for character to transmit */
+#define REG_SIM_IT_SIM_RX (1 << 4) /* 0 = on read access to REG_SIM_DRX */
+ /* 1 = waiting characters to be read */
+
+/* Reg_sim_drx register (R) - FFFE:000A */
+#define REG_SIM_DRX 0xFFFE000A /* register address */
+#define REG_SIM_DRX_SIM_DRX 0 /* next data byte in FIFO available for reading */
+#define REG_SIM_DRX_SIM_DRX_0 1
+#define REG_SIM_DRX_SIM_DRX_1 (1 << 1)
+#define REG_SIM_DRX_SIM_DRX_2 (1 << 2)
+#define REG_SIM_DRX_SIM_DRX_3 (1 << 3)
+#define REG_SIM_DRX_SIM_DRX_4 (1 << 4)
+#define REG_SIM_DRX_SIM_DRX_5 (1 << 5)
+#define REG_SIM_DRX_SIM_DRX_6 (1 << 6)
+#define REG_SIM_DRX_SIM_DRX_7 (1 << 7)
+#define REG_SIM_DRX_SIM_DRX_MASK 0xFF
+#define REG_SIM_DRX_STATRXPAR (1 << 8) /* parity-check for received byte */
+
+/* Reg_sim_dtx register (R/W) - FFFE:000C */
+#define REG_SIM_DTX 0xFFFE000C /* register address */
+#define REG_SIM_DTX_SIM_DTX_0 /* next data byte to be transmitted */
+#define REG_SIM_DTX_SIM_DTX_1
+#define REG_SIM_DTX_SIM_DTX_2
+#define REG_SIM_DTX_SIM_DTX_3
+#define REG_SIM_DTX_SIM_DTX_4
+#define REG_SIM_DTX_SIM_DTX_5
+#define REG_SIM_DTX_SIM_DTX_6
+#define REG_SIM_DTX_SIM_DTX_7
+
+/* Reg_sim_maskit register (R/W) - FFFE:000E */
+#define REG_SIM_MASKIT 0xFFFE000E /* register address */
+#define REG_SIM_MASKIT_MASK_SIM_NATR 1 /* No-answer-to-reset interrupt */
+#define REG_SIM_MASKIT_MASK_SIM_WT (1 << 1) /* Character wait-time overflow interrupt */
+#define REG_SIM_MASKIT_MASK_SIM_OV (1 << 2) /* Receive overflow interrupt */
+#define REG_SIM_MASKIT_MASK_SIM_TX (1 << 3) /* Waiting character to transmit interrupt */
+#define REG_SIM_MASKIT_MASK_SIM_RX (1 << 4) /* Waiting characters to be read interrupt */
+#define REG_SIM_MASKIT_MASK_SIM_CD (1 << 5) /* SIM card insertion/extraction interrupt */
+
+/* Reg_sim_it_cd register (R) - FFFE:0010 */
+#define REG_SIM_IT_CD 0xFFFE0010 /* register address */
+#define REG_SIM_IT_CD_IT_CD 1 /* 0 = on read access to REG_SIM_IT_CD, */
+ /* 1 = SIM card insertion/extraction */
+
+
+#define SIM_DEBUG_OUTPUTDELAY 200 /* Output delay to minimize stress with some uart bugs */
+#define SIM_DEBUG 0 /* 0=Debug messages are off / 1=Debug messages are on */
+#define SIM_OPERATION_DELAY 100 /* Time between operations like reset, vcc apply ect... */
+
+
+void calypso_sim_regdump(void); /* Display Register dump */
+
+int calypso_sim_powerup(uint8_t *atr); /* Apply power to the simcard (see note 1) */
+int calypso_sim_reset(uint8_t *atr); /* reset the simcard (see note 1) */
+
+
+void calypso_sim_powerdown(void); /* Powerdown simcard */
+
+/* APDU transmission modes */
+#define SIM_APDU_PUT 0 /* Transmit a data body to the card */
+#define SIM_APDU_GET 1 /* Fetch data from the card eg. GET RESOPNSE */
+
+/* Transceive T0 Apdu to sim acording to GSM 11.11 Page 34 */
+int calypso_sim_transceive(uint8_t cla, /* Class (in GSM context mostly 0xA0 */
+ uint8_t ins, /* Instruction */
+ uint8_t p1, /* First parameter */
+ uint8_t p2, /* Second parameter */
+ uint8_t p3le, /* Length of the data that should be transceived */
+ uint8_t *data, /* Data payload */
+ uint8_t *status, /* Status word (2 byte array, see note 1) */
+ uint8_t mode); /* Mode of operation: 1=GET, 0=PUT */
+
+ /* Note 1: You can use a null-pointer (0) if you are not interested in
+ the status word */
+
+/* Transmission of raw data */
+int calypso_sim_receive(uint8_t *data); /* Receive raw data through the sim interface */
+int calypso_sim_transmit(uint8_t *data, int length); /* Transmit raw data through the sim interface */
+
+void calypso_sim_init(void); /* Initialize simcard interface */
+
+
+/* Known Bugs:
+ 1.) After powering down the simcard communication stops working
+*/
+
+#endif /* _CALYPSO_SIM_H */
diff --git a/Src/osmocombb/src/target/firmware/include/calypso/timer.h b/Src/osmocombb/src/target/firmware/include/calypso/timer.h
new file mode 100644
index 0000000..694e4eb
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/include/calypso/timer.h
@@ -0,0 +1,25 @@
+#ifndef _CAL_TIMER_H
+#define _CAL_TIMER_H
+
+/* Enable or Disable a timer */
+void hwtimer_enable(int num, int on);
+
+/* Configure pre-scaler and if timer is auto-reload */
+void hwtimer_config(int num, uint8_t pre_scale, int auto_reload);
+
+/* Load a timer with the given value */
+void hwtimer_load(int num, uint16_t val);
+
+/* Read the current timer value */
+uint16_t hwtimer_read(int num);
+
+/* Enable or disable the watchdog */
+void wdog_enable(int on);
+
+/* Reset cpu using watchdog */
+void wdog_reset(void);
+
+/* power up the timers */
+void hwtimer_init(void);
+
+#endif /* _CAL_TIMER_H */
diff --git a/Src/osmocombb/src/target/firmware/include/calypso/tpu.h b/Src/osmocombb/src/target/firmware/include/calypso/tpu.h
new file mode 100644
index 0000000..3b1b600
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/include/calypso/tpu.h
@@ -0,0 +1,122 @@
+#ifndef _CALYPSO_TPU_H
+#define _CALYPSO_TPU_H
+
+#define BITS_PER_TDMA 1250
+#define QBITS_PER_TDMA (BITS_PER_TDMA * 4) /* 5000 */
+#define TPU_RANGE QBITS_PER_TDMA
+#define SWITCH_TIME (TPU_RANGE-10)
+
+/* Assert or de-assert TPU reset */
+void tpu_reset(int active);
+/* Enable or Disable a new scenario loaded into the TPU */
+void tpu_enable(int active);
+/* Enable or Disable the clock of the TPU Module */
+void tpu_clk_enable(int active);
+/* Enable Frame Interrupt generation on next frame. DSP will reset it */
+void tpu_dsp_frameirq_enable(void);
+/* Is a Frame interrupt still pending for the DSP ? */
+int tpu_dsp_fameirq_pending(void);
+/* Rewind the TPU, i.e. restart enqueueing instructions at the base addr */
+void tpu_rewind(void);
+/* Enqueue a raw TPU instruction */
+void tpu_enqueue(uint16_t instr);
+/* Initialize TPU and TPU driver */
+void tpu_init(void);
+/* (Busy)Wait until TPU is idle */
+void tpu_wait_idle(void);
+/* Enable FRAME interrupt generation */
+void tpu_frame_irq_en(int mcu, int dsp);
+/* Force the generation of a DSP interrupt */
+void tpu_force_dsp_frame_irq(void);
+
+/* Get the current TPU SYNCHRO register */
+uint16_t tpu_get_synchro(void);
+/* Get the current TPU OFFSET register */
+uint16_t tpu_get_offset(void);
+
+enum tpu_instr {
+ TPU_INSTR_AT = (1 << 13),
+ TPU_INSTR_OFFSET = (2 << 13),
+ TPU_INSTR_SYNCHRO = (3 << 13), /* Loading delta synchro value in TPU synchro register */
+ TPU_INSTR_WAIT = (5 << 13), /* Wait a certain period (in GSM qbits) */
+ TPU_INSTR_SLEEP = (0 << 13), /* Stop the sequencer by disabling TPU ENABLE bit in ctrl reg */
+ /* data processing */
+ TPU_INSTR_MOVE = (4 << 13),
+};
+
+/* Addresses internal to the TPU, only accessible via MOVE */
+enum tpu_reg_int {
+ TPUI_TSP_CTRL1 = 0x00,
+ TPUI_TSP_CTRL2 = 0x01,
+ TPUI_TX_1 = 0x04,
+ TPUI_TX_2 = 0x03,
+ TPUI_TX_3 = 0x02,
+ TPUI_TX_4 = 0x05,
+ TPUI_TSP_ACT_L = 0x06,
+ TPUI_TSP_ACT_U = 0x07,
+ TPUI_TSP_SET1 = 0x09,
+ TPUI_TSP_SET2 = 0x0a,
+ TPUI_TSP_SET3 = 0x0b,
+ TPUI_DSP_INT_PG = 0x10,
+ TPUI_GAUGING_EN = 0x11,
+};
+
+enum tpui_ctrl2_bits {
+ TPUI_CTRL2_RD = (1 << 0),
+ TPUI_CTRL2_WR = (1 << 1),
+};
+
+static inline uint16_t tpu_mod5000(int16_t time)
+{
+ if (time < 0)
+ return time + 5000;
+ if (time >= 5000)
+ return time - 5000;
+ return time;
+}
+
+/* Enqueue a SLEEP operation (stop sequencer by disabling TPU ENABLE bit) */
+static inline void tpu_enq_sleep(void)
+{
+ tpu_enqueue(TPU_INSTR_SLEEP);
+}
+
+/* Enqueue a MOVE operation */
+static inline void tpu_enq_move(uint8_t addr, uint8_t data)
+{
+ tpu_enqueue(TPU_INSTR_MOVE | (data << 5) | (addr & 0x1f));
+}
+
+/* Enqueue an AT operation */
+static inline void tpu_enq_at(int16_t time)
+{
+ tpu_enqueue(TPU_INSTR_AT | tpu_mod5000(time));
+}
+
+/* Enqueue a SYNC operation */
+static inline void tpu_enq_sync(int16_t time)
+{
+ tpu_enqueue(TPU_INSTR_SYNCHRO | time);
+}
+
+/* Enqueue a WAIT operation */
+static inline void tpu_enq_wait(int16_t time)
+{
+ tpu_enqueue(TPU_INSTR_WAIT | time);
+}
+
+/* Enqueue an OFFSET operation */
+static inline void tpu_enq_offset(int16_t time)
+{
+ tpu_enqueue(TPU_INSTR_OFFSET | time);
+}
+
+static inline void tpu_enq_dsp_irq(void)
+{
+ tpu_enq_move(TPUI_DSP_INT_PG, 0x0001);
+}
+
+/* add two numbers, modulo 5000, and ensure the result is positive */
+uint16_t add_mod5000(int16_t a, int16_t b);
+
+#endif /* _CALYPSO_TPU_H */
diff --git a/Src/osmocombb/src/target/firmware/include/calypso/tsp.h b/Src/osmocombb/src/target/firmware/include/calypso/tsp.h
new file mode 100644
index 0000000..d58a562
--- /dev/null
+++ b/Src/osmocombb/src/target/firmware/include/calypso/tsp.h
@@ -0,0 +1,31 @@
+#ifndef _CALYPSO_TSP_H
+#define _CALYPSO_TSP_H
+
+#define TSPACT(x) (1 << x)
+#define TSPEN(x) (x)
+
+/* initiate a TSP write through the TPU */
+void tsp_write(uint8_t dev_idx, uint8_t bitlen, uint32_t dout);
+
+/* Configure clock edge and chip enable polarity for a device */
+void tsp_setup(uint8_t dev_idx, int clk_rising, int en_positive, int en_edge);
+
+/* Obtain the current tspact state */
+uint16_t tsp_act_state(void);
+
+/* Update the TSPACT state, including enable and disable */
+void tsp_act_update(uint16_t new_act);
+
+/* Enable one or multiple TSPACT signals */
+void tsp_act_enable(uint16_t bitmask);
+
+/* Disable one or multiple TSPACT signals */
+void tsp_act_disable(uint16_t bitmask);
+
+/* Toggle one or multiple TSPACT signals */
+void tsp_act_toggle(uint16_t bitmask);
+
+/* Initialize TSP driver */
+void tsp_init(void);
+
+#endif /* _CALYPSO_TSP_H */